Counter-Based Time-to-Digital Converter for Low Flicker Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing time-to-digital converters (TDCs) face challenges in achieving low flicker noise, which is crucial for applications like cellular base stations that require precise phase noise control, as they are often limited by the flicker noise of flip-flops used in the circuit.
Innovation Solution
A counter-based TDC circuit is designed with a logic gate, synchronization circuit, and a ripple counter to determine the time difference between clock edges, utilizing a low flicker noise clock source and generating start and stop signals for the counter, thereby minimizing noise to be less than the quantizing step of the TDC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional flip-flop based TDC is used, then device complexity is reduced, but measurement precision deteriorates due to flicker noise
Solution Approach 1:
The TDC is segmented into distinct functional modules: a synchronization circuit that generates start/stop signals, a counter circuit that performs the time measurement, and a digital interface. This segmentation allows each module to be optimized independently, with the counter circuit using low-flicker-noise clocking to achieve high precision without requiring complex noise cancellation circuits throughout the entire system.
Solution Approach 2:
A synchronization circuit acts as an intermediary between the input trigger signals and the counter circuit. This intermediary generates precise start and stop signals for the counter using a low flicker noise clock, isolating the measurement process from the flicker noise inherent in direct flip-flop based TDC designs and enabling higher measurement precision.
2Measurement precision
If counter-based TDC with synchronization circuit is used, then measurement precision improves, but device complexity increases
Solution Approach 1:
The counter circuit is self-synchronized using its own internal low flicker noise clock, eliminating the need for external synchronization mechanisms or complex calibration circuits. The synchronization circuit automatically generates the necessary start and stop signals based on the clock edges, making the system self-contained and reducing overall complexity despite the added precision capabilities.
3Measurement precision
If low flicker noise clock source is used, then measurement precision improves, but use of energy increases
Solution Approach 1:
The system changes the clock frequency parameter dynamically - using a higher frequency low-flicker-noise clock only during the brief measurement interval when start and stop signals are active. The counter is disabled between measurements, and the synchronization circuit operates intermittently, reducing overall power consumption while maintaining high precision during active measurement periods.
Data Source
AI summary
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.