Counter Timer Match Dithering for Sub-Clock Resolution

Solution Overview

Problem

Traditional counter/timer circuits have limited timer match resolution, which is insufficient for applications requiring higher precision, and increasing the counter clock rate is often not feasible.

Innovation Solution

Incorporating a dither module that delays the assertion of the match condition based on a value programmed in a match companion register, allowing for a fractional portion of the timer/counter match values and increasing the average resolution to 1/Mth of a clock period through an event-based timer match dither technique.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the counter clock rate is increased to improve timer match resolution, then measurement precision is improved, but device complexity and feasibility deteriorate

Engineering Contradiction:

Improvetimer match resolutionVSAvoidcounter clock rate requirements

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the timer match resolution into two components: an integer portion stored in the match register and a fractional portion stored in the match companion register. This segmentation allows the system to achieve sub-clock-period resolution without increasing the clock rate, as the fractional portion (M bits) provides the additional precision bits. The match decision is made by comparing both the integer and fractional portions, effectively dividing the resolution requirement into manageable parts that don't demand higher clock frequencies.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds another dimension to the match comparison by introducing the match companion register that stores fractional portions. Instead of relying solely on the integer match register, the system now operates in a two-dimensional space: integer match values and fractional match values. This dimensional expansion allows the timer to achieve M bits of fractional resolution without increasing the clock rate, as the fractional dimension provides the additional precision needed.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Measurement precision

If the counter clock rate is increased to achieve higher timer match resolution, then measurement precision is improved, but power consumption increases

Engineering Contradiction:

Improvetimer match resolutionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent segments the timer match resolution into two components: an integer portion stored in the match register and a fractional portion stored in the match companion register. This segmentation allows the system to achieve sub-clock-period resolution without increasing the clock rate, as the fractional portion (M bits) provides the additional precision bits. The match decision is made by comparing both the integer and fractional portions, effectively dividing the resolution requirement into manageable parts that don't demand higher clock frequencies.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds another dimension to the match comparison by introducing the match companion register that stores fractional portions. Instead of relying solely on the integer match register, the system now operates in a two-dimensional space: integer match values and fractional match values. This dimensional expansion allows the timer to achieve M bits of fractional resolution without increasing the clock rate, as the fractional dimension provides the additional precision needed.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Device complexity

If traditional match registers are used, then device complexity is kept simple, but measurement precision is insufficient for high-resolution applications

Engineering Contradiction:

Improveregister structureVSAvoidtimer match resolution

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the timer match resolution into two components: an integer portion stored in the match register and a fractional portion stored in the match companion register. This segmentation allows the system to achieve sub-clock-period resolution without increasing the clock rate, as the fractional portion (M bits) provides the additional precision bits. The match decision is made by comparing both the integer and fractional portions, effectively dividing the resolution requirement into manageable parts that don't demand higher clock frequencies.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds another dimension to the match comparison by introducing the match companion register that stores fractional portions. Instead of relying solely on the integer match register, the system now operates in a two-dimensional space: integer match values and fractional match values. This dimensional expansion allows the timer to achieve M bits of fractional resolution without increasing the clock rate, as the fractional dimension provides the additional precision needed.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8719749B2Timer match dithering

Publication Date: 2014.05.06 NXP BV

AI summary

A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.