Counterless Pipelined Processor for Compact IC Design
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Solution Overview
Problem
Conventional pipelined processors require substantial integrated circuit area due to the presence of an instruction counter and associated control circuitry, limiting their compact implementation and efficiency.
Innovation Solution
A pipelined run-to-completion processor design that omits the instruction counter, initiating instruction fetching only through external input data or initial fetch information, allowing for a compact implementation of approximately ten thousand equivalent gates. This processor includes a lookup table circuit to determine memory addresses and executes a novel pop stack absolute instruction, enabling modular code execution across multiple tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an instruction counter and associated control circuitry are included in a pipelined processor, then the processor can automatically track and fetch instructions sequentially, but the integrated circuit area becomes substantial and complex
Solution Approach 1:
The patent removes the instruction counter and its associated control circuitry from the processor design. Instead of automatically tracking instruction addresses, the system extracts this functionality by using external input data values to directly provide fetch information, eliminating the need for dedicated counter hardware and reducing circuit area significantly
Solution Approach 2:
The input data value register serves multiple functions: it stores input data values for processing and simultaneously provides fetch information for instruction retrieval. This multi-functionality eliminates the need for separate instruction counter circuitry, as the same hardware structure serves dual purposes in both data processing and control flow management
2Extent of automation
If an instruction counter and control circuitry are implemented, then instruction fetching can be automated, but the device complexity increases substantially
Solution Approach 1:
The patent extracts the automation functionality from dedicated counter circuitry and redistributes it across existing processor components. The sequence generator uses simple logic to increment fetch information based on execution outcomes, while the input data value register provides the base address, collectively achieving automated instruction fetching without complex control circuitry
Solution Approach 2:
The patent merges the instruction fetching control logic with the existing execution flow control. The sequence generator that manages instruction sequencing is integrated with the same control structures that manage data processing, combining multiple control functions into unified logic that reduces overall device complexity while maintaining automation
3Speed
If the processor fetches instructions continuously, then execution speed is maintained, but power consumption increases
Solution Approach 1:
The processor implements periodic instruction fetching triggered by external input data arrivals rather than continuous clocked operation. The sequence generator increments fetch information only when needed, and the processor enters idle states between input arrivals, creating a periodic execution pattern that maintains speed when active while reducing power consumption during idle periods
Solution Approach 2:
The processor dynamically adjusts its operation mode based on input data availability. When input data arrives, the processor actively fetches and executes instructions at full speed; when no input is pending, the processor reduces activity, allowing dynamic power management that balances execution speed requirements with power consumption constraints
Data Source
AI summary
A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.