Counterless Run-to-Completion Processor Design
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Solution Overview
Problem
Conventional pipelined processors require substantial integrated circuit area due to the presence of an instruction counter and associated control circuitry, limiting their compact implementation and efficiency.
Innovation Solution
A pipelined run-to-completion processor design that omits the instruction counter and uses incoming input data values or initial fetch information to initiate instruction fetching, employing a lookup table circuit to determine memory addresses and executing a 'finished' instruction to stop processing, along with a novel pop stack absolute instruction that operates independently of the stack pointer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an instruction counter and associated control circuitry are included in a pipelined processor, then the processor can automatically track and fetch instructions sequentially, but the integrated circuit area increases substantially
Solution Approach 1:
The patent removes the instruction counter and its associated control circuitry from the processor architecture. Instead of automatic sequential tracking, the processor relies on external entities (host processor or firmware) to provide fetch addresses, thereby eliminating the circuitry that would otherwise occupy substantial integrated circuit area.
Solution Approach 2:
The patent introduces an intermediary mechanism where external entities (host processor or firmware) act as mediators to provide instruction fetch addresses to the processor. This external address provision replaces the internal instruction counter function, allowing the processor to maintain compact design while still enabling sequential instruction execution through external control.
2Area of stationary object
If the processor is designed to be compact with minimal circuitry, then the integrated circuit area is reduced, but the processor lacks automatic instruction fetching capability
Solution Approach 1:
The processor is designed to be self-service in the sense that it can execute instructions efficiently once fetched, using its internal pipeline architecture to process multiple instructions simultaneously without requiring complex control circuitry for fetching. The compact design achieves productivity through pipeline parallelism rather than automatic fetching.
Solution Approach 2:
The patent employs preliminary action by having fetch addresses pre-determined and provided by external entities before the processor needs to execute instructions. This allows the compact processor to receive ready-made fetch addresses, eliminating the need for internal address generation circuitry while maintaining efficient instruction execution through the pipeline.
3Extent of automation
If conventional control circuitry is used to manage instruction fetching, then instruction execution is automated, but power consumption increases
Solution Approach 1:
The patent extracts the automated instruction fetching function from the processor's internal control circuitry and relocates it to external entities. This removal of the instruction counter and associated control logic directly reduces the stationary circuitry that would otherwise consume power continuously, while instruction execution remains automated through external address provision.
Data Source
AI summary
A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.