Countersunk Via Hole Plating for PCB Wrap Integrity
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Solution Overview
Problem
Current methods for producing multilayer printed circuit boards with via holes face issues of conductor separation and inconsistent plating, leading to reliability problems and increased production costs due to material loss and uneven surfaces, particularly with clearance etching methods.
Innovation Solution
A method involving countersinking the via holes to create a beveled opening, allowing for precise plating and reducing the need for additional plating steps, which results in consistent and uniform conductive layers and eliminates the need for clearance etching, thereby enhancing via wrap integrity and reducing material loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clearance etching is used to prevent conductor separation, then via wrap integrity is improved, but material loss increases and manufacturing complexity increases
Solution Approach 1:
The via holes are countersunk before plating operations, creating a beveled opening that prevents conductor separation at the surface. This preliminary geometric modification eliminates the need for subsequent clearance etching to achieve wrap integrity, thereby preventing material loss while ensuring reliable via connections
Solution Approach 2:
The harmful clearance etching step is completely removed from the manufacturing process. By countersinking via holes beforehand, the patent extracts the unnecessary material removal step that caused both material loss and increased manufacturing complexity, while still achieving the desired via wrap integrity
2Manufacturing precision
If multiple plating steps are used to ensure uniform conductive layers, then plating consistency is improved, but manufacturing time increases and process complexity increases
Solution Approach 1:
The via holes are countersunk before plating operations, creating a beveled opening that ensures uniform plating deposition in a single step. This preliminary geometric preparation eliminates the need for multiple plating steps, achieving both consistent conductive layers and reduced manufacturing time
Solution Approach 2:
The patent changes the geometric parameters of the via hole opening by creating a beveled shape through countersinking. This parameter modification allows for uniform plating deposition in a single operation, eliminating the need for multiple plating steps while maintaining consistent conductive layer thickness
3Ease of manufacture
If conventional drilling is used to create via holes, then manufacturing simplicity is maintained, but conductor separation occurs and via wrap integrity deteriorates
Solution Approach 1:
The via holes are countersunk immediately after drilling, creating a beveled opening that prevents conductor separation. This simple preliminary action modifies the via hole geometry to ensure proper wrap integrity without requiring complex manufacturing processes
Solution Approach 2:
The patent introduces asymmetry by creating a beveled opening in the via hole through countersinking. This asymmetric geometry, with the larger opening at the surface and smaller diameter deeper in the substrate, prevents conductor separation and ensures proper via wrap integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and uniform plating, improves via wrap integrity, reduces material loss, and allows for the production of printed circuit boards with finer features and tighter geometries, enhancing the reliability and cost-effectiveness of the manufacturing process.
Implementation Method 1
The first end of the via hole formed in the first foil layer is countersunk to form a beveled opening at the surface. The countersinking of the via hole angularly removes the foil layer (surface copper) from around the hole opening.
Implementation Method 2
After the conductive coating is applied to the sidewall of the via hole and the one or more countersunk surfaces
Data Source
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AI summary
A printed circuit board (PCB) has one or more filled and plated vias formed from a countersunk via hole. A laminated substrate is formed and one or more via holes are made therein. The ends of the one or more via holes are then countersunk. The sidewall of the one or more via holes and the countersunk surfaces of the one or more via holes are plated with a conductive material. The laminated substrate including the one or more counter-sunk and plated via holes is processed in conventional fashion, including filling of the one or more via holes. A conductive cap layer is preferably formed over both ends of the plated via hole having fill composition.