Coupled DPLL Offset Register for Hitless Re-Arrangements
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Solution Overview
Problem
In systems of coupled digital phase-locked loops (DPLLs), rapid changes in frequency offset during re-arrangements cause significant phase transients on the output, which existing mechanisms fail to mitigate effectively.
Innovation Solution
An apparatus comprising an accumulator circuit and an offset register that combines frequency offset values from multiple sourcing DPLLs, allowing for a smooth transition by presenting a stored offset value during re-arrangements, thereby reducing phase transients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a receiving DPLL switches from one sourcing DPLL to another sourcing DPLL or if a sourcing DPLL switches to another input reference clock with a different fractional frequency offset, then the system gains adaptability and flexibility in clock sourcing, but the added frequency offset incurs a rapid change that causes a large phase transient on the output of the receiving DPLL
Solution Approach 1:
The offset register stores the previous frequency offset value before a switch occurs. When a DPLL switching event is detected, the system uses the pre-stored offset value to calculate a transitional offset, allowing the receiving DPLL to anticipate and prepare for the frequency change rather than reacting to it abruptly.
Solution Approach 2:
The apparatus calculates a transitional frequency offset by combining the stored previous offset with the new offset from the accumulator circuit. This transitional value acts as a cushion that absorbs the abrupt change, preventing the large phase transient that would otherwise occur during DPLL re-arrangement.
2Speed
If the receiving DPLL immediately updates the frequency offset when a sourcing DPLL switches, then the system responds quickly to changes, but this causes a rapid frequency offset change that generates phase transient on the output
Solution Approach 1:
The offset register serves as an intermediary element between the accumulator circuit and the receiving DPLL. Instead of directly updating with the new offset value, the system uses the stored previous offset as an intermediate step, allowing the frequency transition to occur smoothly without generating harmful phase transients.
Solution Approach 2:
The system changes the parameter update strategy by not immediately updating the frequency offset to its new value. Instead, it uses a calculated transitional offset that combines the previous stored value with the new offset, thereby changing how the parameter transitions and eliminating the harmful phase transient effect.
Data Source
AI summary
An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.