Coupled DPLL Offset Compensation for Hitless Re-Arrangement
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Solution Overview
Problem
In systems of coupled digital phase-locked loops (DPLLs), rapid changes in frequency offset during re-arrangements cause significant phase transients on the output, which existing mechanisms fail to mitigate effectively.
Innovation Solution
An apparatus comprising an accumulator circuit and an offset register that combines frequency offset values from multiple sourcing DPLLs, allowing for a smooth transition by presenting an updated offset value during re-arrangements, thereby reducing phase transients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a receiving DPLL switches from one sourcing DPLL to another sourcing DPLL, or if a sourcing DPLL switches to another input reference clock with a different fractional frequency offset, then the system gains adaptability and flexibility in clock sourcing, but the added frequency offset incurs a rapid change that causes a large phase transient on the output of the receiving DPLL
Solution Approach 1:
The apparatus performs preliminary action by calculating the updated offset value in advance before the actual DPLL re-arrangement occurs. The offset register is pre-loaded with the pre-calculated updated offset value, so that when the re-arrangement happens, the receiving DPLL can immediately use the correct offset without experiencing a rapid frequency offset change. This prevents phase transients while maintaining the ability to switch between different sourcing DPLLs and reference clocks.
Solution Approach 2:
The apparatus introduces an intermediary mechanism consisting of the offset register and the updated offset value calculation logic. This intermediary absorbs and compensates for the frequency offset differences between different sourcing DPLLs and reference clocks. By inserting this intermediate compensation layer, the system can switch between different sources without directly exposing the receiving DPLL to abrupt frequency offset changes, thus maintaining output phase stability while enabling flexible re-arrangements.
2Speed
If the receiving DPLL immediately updates the frequency offset upon re-arrangement, then the system responds quickly to changes, but this causes a large phase transient on the output
Solution Approach 1:
The apparatus converts the potentially harmful rapid frequency offset change into a benefit by pre-calculating the updated offset value and storing it in the offset register before the re-arrangement occurs. The harmful rapid transition is transformed into a smooth, pre-prepared switch. The system maintains fast response by having the updated value ready in advance, while the phase transient is eliminated because the receiving DPLL switches to a pre-computed value rather than experiencing a sudden change.
3Stability of the object's composition
If the system maintains the current frequency offset during re-arrangement, then phase stability is preserved, but the frequency offset becomes outdated and inaccurate after the re-arrangement
Solution Approach 1:
The apparatus resolves this contradiction by performing preliminary calculation of the updated offset value before the re-arrangement occurs. The offset register is pre-loaded with the accurate updated offset value that reflects the new sourcing configuration. This allows the system to maintain phase stability during the transition while ensuring the frequency offset is already accurate for the new configuration, eliminating the need to choose between stability and accuracy.
Data Source
AI summary
An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.