Coupled FPGA Lookup Tables for Fast Function Reconfiguration
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Solution Overview
Problem
Existing field programmable gate arrays (FPGAs) are limited by the time it takes to load lookup table configurations, which restricts the frequency at which functions can be changed, and this process consumes significant power due to the need to cycle power for each configuration change.
Innovation Solution
Coupling logic blocks in FPGAs allows direct transfer of lookup table configurations between adjacent blocks, reducing the time needed to change functions and minimizing power consumption by using non-volatile CMOS-based memory cells that can copy configuration bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lookup table configurations are loaded when the FPGA is powered up, then the configuration process is simple, but the time needed to change functions is long and power consumption is high
Solution Approach 1:
The patent applies preliminary action by pre-loading configuration data into coupled lookup tables during manufacturing or initial setup. The coupled LUTs store configuration bits that can be rapidly transferred between adjacent logic blocks without requiring full power cycling, enabling fast function changes while maintaining configuration simplicity
Solution Approach 2:
The patent uses copying by transferring configuration data between coupled lookup tables in adjacent logic blocks. When a function change is needed, configuration bits are copied from one LUT to another through direct coupling, eliminating the need to reload configurations from external memory and significantly reducing reconfiguration time
2Ease of operation
If lookup table configurations are loaded when the FPGA is powered up, then the system is simple to operate, but power consumption increases due to frequent power cycling
Solution Approach 1:
Configuration data is preliminarily loaded into coupled lookup tables during manufacturing or initial setup. This allows the FPGA to perform function changes by transferring data between pre-loaded LUTs without cycling power, dramatically reducing power consumption while maintaining ease of operation
Solution Approach 2:
The system copies configuration bits between coupled lookup tables instead of reloading from external memory. This copying mechanism enables fast function changes with minimal power consumption since it avoids the high-power state associated with full configuration reloading and power cycling
3Productivity
If configuration data is transferred between logic blocks, then function change speed increases to millions or billions of times per second, but the device complexity increases
Solution Approach 1:
The patent segments the FPGA into logic blocks with coupled lookup tables. Each LUT is divided into multiple coupled units that can independently store and transfer configuration data. This segmentation enables parallel configuration transfers between adjacent blocks, achieving high function change frequencies while managing complexity through modular organization
Solution Approach 2:
The patent merges adjacent lookup tables into coupled units where configuration data can be shared and transferred between them. By combining the functionality of multiple LUTs into coupled groups, the system achieves high-speed reconfiguration through coordinated data transfer while reducing the overall complexity compared to fully independent blocks
Data Source
AI summary
A field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.