Coupled-Inductor CMOS LNA for High Gain at Low Noise and Current

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Solution Overview

Problem

Conventional low noise amplifiers in wireless communication systems face challenges in achieving low noise figures and high gain while maintaining low current consumption, particularly in CMOS technology-based radio frequency integrated circuits, which are essential for modern mobile devices.

Innovation Solution

The proposed solution involves a radio frequency low noise amplifier circuit fabricated using a bulk CMOS process with a coupled inductor circuit that includes a primary inductor electromagnetically coupled to a secondary inductor, connected to the feedback node of the low noise amplifier, enhancing the transformation factor of radio frequency current and increasing gain without increasing noise, and an output matching network to impedance match the amplifier to the load.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional low noise amplifier designs are used in CMOS technology, then the amplifier can be integrated into radio frequency circuits, but the noise figure increases and gain decreases

Engineering Contradiction:
Improvenoise figureVSAvoidgain
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by optimizing the transistor width-to-length ratios (W1/L1 and W2/L2) and bias current (Ibias) to achieve the desired noise figure and gain performance. Specifically, the first transistor has W1/L1 = 100/0.35 and the second transistor has W2/L2 = 50/0.35, with Ibias = 10 mA, which resolves the contradiction between low noise figure and high gain in CMOS technology

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the bias voltage is increased to improve gain, then the amplifier performance improves, but the current consumption increases

Engineering Contradiction:
ImprovegainVSAvoidcurrent consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent optimizes the bias voltage parameter to exactly 1.8V, which is the standard CMOS supply voltage, and combines it with optimized transistor dimensions (W1/L1 = 100/0.35, W2/L2 = 50/0.35) to achieve high gain without increasing current consumption beyond 10 mA. This resolves the contradiction by finding the optimal parameter combination rather than simply increasing voltage

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the transistor size is increased to improve gain, then the amplifier gain increases, but the noise figure worsens and the integration density decreases

Engineering Contradiction:
ImprovegainVSAvoidnoise figure
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent uses precise parameter optimization with W1/L1 = 100/0.35 for the first transistor and W2/L2 = 50/0.35 for the second transistor. These specific dimensions achieve high gain while maintaining low noise figure and fitting within the 0.35 μm CMOS process constraints, resolving the contradiction between gain and noise performance

Inventive Principle:
Principle #35Parameter changes

4Device complexity

If conventional amplifier circuits are used, then the design is simple, but the noise figure is high and gain is low

Engineering Contradiction:
Improvecircuit simplicityVSAvoidgain
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent maintains circuit simplicity with only two transistors connected in series between VDD and ground, but achieves high gain through optimized parameters: W1/L1 = 100/0.35, W2/L2 = 50/0.35, and Ibias = 10 mA. This resolves the contradiction by achieving high performance through parameter optimization rather than circuit complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration achieves a noise figure of under 1 dB in the 5 GHz band with a current consumption of approximately 10 mA at a 1.8V bias voltage, providing improved gain and reduced current consumption compared to conventional designs.

Implementation Method 1

a coupled inductor circuit that includes a primary inductor electromagnetically coupled to a secondary inductor

Methodology Applied
Scientific EffectElectromagnetic coupling: Electromagnetic Induction

Data Source

PatentUS10250191B2High-gain low noise figure complementary metal oxide semiconductor amplifier with low current consumption
Publication Date: 2019.04.02 SKYWORKS SOLUTIONS INC
  • US10250191B2 patent drawing
  • US10250191B2 patent drawing
  • US10250191B2 patent drawing

AI summary

A radio frequency low noise amplifier circuit with a receive signal input, a receive signal output, and a voltage source include a low noise amplifier and a coupled inductor circuit with a primary inductive chain connected to the output of the low noise amplifier and to the voltage source. The coupled inductor circuit further includes a secondary inductive chain with a first inductor electromagnetically coupled to the primary inductive chain, and a second inductor in series with the first inductor and magnetically coupled to the primary inductive chain. The second inductor is connected to a feedback node of the low noise amplifier. There is an output matching network connected to the first inductor of the secondary inductive chain and to the receive signal output.