Monolithic Two-Phase Coupled-Inductor for Compact Power Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power electronic circuits, such as SMPS and IVR, face limitations in power efficiency and size due to magnetically induction devices, which result in short battery life and bulky size, especially in mobile devices, and two-phase power converter designs using coupled-inductors increase chip footprint area while requiring improved magnetic coupling.
Innovation Solution
The development of monolithically compact two-phase coupled-inductor devices with a center insulator layer sandwiched by top and bottom substrates, where top and bottom inductors are symmetrically disposed as mirror images, and the use of air core or magnetic core configurations to enhance magnetic coupling without increasing footprint area, achieved through deep trench formation and conductive material deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If two-phase power converter designs using coupled-inductors are used, then power conversion efficiency is improved, but chip footprint area increases
Solution Approach 1:
The patent transitions from planar inductor layouts to three-dimensional stacked coupled-inductor structures. By vertically stacking multiple inductor layers with magnetic coupling through the substrate, the design achieves high power conversion efficiency while maintaining a compact chip footprint, effectively moving the solution into the vertical dimension.
Solution Approach 2:
The patent implements nested inductor structures where multiple inductor windings are coupled through a shared magnetic path or substrate. The coupled-inductors are arranged such that one inductor is effectively nested within or alongside another, sharing common magnetic flux paths, which improves efficiency while minimizing the required chip area.
2Area of stationary object
If inductor size is reduced for compact devices, then device size is minimized, but power efficiency deteriorates
Solution Approach 1:
The patent enhances the magnetic coupling region between stacked inductors through localized magnetic core structures or optimized spacing in specific areas. By concentrating magnetic flux paths in targeted regions between inductor layers, the design achieves high efficiency in a compact form factor without requiring uniform enlargement of the entire device.
Solution Approach 2:
The patent employs composite magnetic structures combining different magnetic materials with varying permeabilities to optimize the coupling between inductors. By using materials with tailored magnetic properties in strategic locations, the design achieves high power efficiency while maintaining compact dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves power conversion efficiency by reducing inductor losses and maintaining a compact size, achieving high inductance density and coupling coefficients while minimizing DC resistance, thus extending battery life and reducing device size.
Implementation Method 1
Both sides of the wafer are electroplated simultaneously to fill both deep trenches with a conductive material
Implementation Method 2
The top inductor is configured to be magnetically coupled across the center insulator layer to the bottom inductor
Data Source
AI summary
Devices and methods of forming a device are disclosed. The method includes providing a wafer that includes a center insulator layer sandwiched by a top substrate and a bottom substrate. Both sides of the wafer are patterned and etched in sequence to form deep trenches in both substrates. A conductive seed layer is formed on both sides of the wafer in sequence to cover all exposed areas. Both sides of the wafer are electroplated simultaneously to fill both deep trenches with a conductive material. Both sides of the wafer are polished in sequence to form a coplanar surface. A protective layer is deposited on both sides of the wafer in sequence. Selective portions of the protective layer on both sides are patterned and etched in sequence to expose micro bump bonding areas. Micro bumps are formed on both sides of the wafer in sequence to facilitate electrical connection.