3D Stacked Coupled Inductors Using Solder Caps
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Solution Overview
Problem
The challenge in integrated circuit (IC) device design is to implement coupled inductors with reduced area requirements without the limitations of metal and silicon thickness, which affects the functionality and efficiency of components like voltage regulators.
Innovation Solution
The method involves using interconnecting elements with solder caps on substrates to form coupled inductors, allowing for compact design and high coupling coefficients by separating inductor spirals with a small distance, thus avoiding the need for additional silicon layers or thick metal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If coupled inductors are implemented on the same layer in an IC device, then the layout area can be reduced, but the coupling coefficient between the two inductors becomes low since only a portion of the magnetic flux from one inductor can be picked up by the other
Solution Approach 1:
The patent transitions from planar (2D) inductor implementation to three-dimensional (3D) stacked inductor implementation. The first and second inductors are formed in different metal layers (M5 and M6) vertically stacked on top of each other, utilizing the vertical dimension to achieve both compact area footprint and strong magnetic coupling through direct proximity and flux linkage.
2Reliability
If coupled inductors are implemented on two different layers in an IC device, then the coupling coefficient may be improved, but the layout area still requires precious die area and lots of turns of the coils for sufficient inductance
Solution Approach 1:
The patent implements nested inductor structures where the first inductor coil is formed in metal layer M5 and the second inductor coil is formed in metal layer M6 directly above it, creating a vertically nested configuration. This nesting approach maximizes spatial utilization and magnetic coupling while minimizing the horizontal footprint area.
Solution Approach 2:
The solution utilizes the vertical dimension by stacking inductors in adjacent metal layers (M5 and M6) rather than placing them side-by-side in the same layer. This 3D stacking approach reduces the horizontal layout area while maintaining sufficient coupling through vertical flux linkage.
3Area of stationary object
If inductors are implemented using deep trenches in a silicon interposer, then the area may be small, but more complex fabrication processes would be necessary and additional silicon wafer cost would be incurred
Solution Approach 1:
The patent utilizes existing metal layers (M5 and M6) in the standard IC fabrication process to form inductors, making the metal layers serve dual purposes: both as interconnect layers and as inductor coil layers. This eliminates the need for separate deep trench fabrication processes and additional silicon interposer processing, reducing overall fabrication complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of coupled inductors in IC devices with reduced area requirements, improved coupling efficiency, and cost-effectiveness, suitable for various industrial applications including microprocessors and high-voltage technology nodes.
Implementation Method 1
forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other
Data Source
AI summary
Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.