Coupled Level Shifter Circuit for Sub-1 ns Voltage Conversion
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Solution Overview
Problem
Existing level shifters in integrated circuits are limited by switching times greater than 1 ns and can fail with low supply voltage, unable to efficiently convert digital signals between different voltage domains.
Innovation Solution
An improved level shifter design incorporating a coupling stage and a level-switching stage, utilizing NMOS and PMOS transistors with capacitors to achieve faster switching times by oscillating node voltages between VDDL and 2*VDDL, enabling switching times below 1 ns while using standard core power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If prior art level shifter designs are used, then the circuit can operate with standard power supply voltages, but the switching time is limited to greater than 1 ns
Solution Approach 1:
The patent changes the voltage parameter by generating a switched voltage that oscillates between VDDL and 2*VDDL, exceeding the standard supply voltage. This parameter change enables faster switching times below 1 ns while maintaining operational reliability through controlled voltage regulation and proper transistor sizing ratios.
2Use of energy by moving object
If low supply voltage VDDL is used, then power consumption is reduced, but the level shifter can fail altogether due to insufficient peak voltage
Solution Approach 1:
The patent implements periodic action through the coupling stage that generates switched voltage oscillating between VDDL and 2*VDDL. This periodic voltage enhancement provides sufficient peak voltage for reliable transistor switching while maintaining low average power consumption through duty cycle control and efficient charge transfer.
3Speed
If transistor current driving capability is increased to reduce switching time, then switching speed improves, but variability in transistor performance increases
Solution Approach 1:
The patent applies asymmetry by using different transistor sizing ratios in the coupling stage versus the level-shifting stage. The coupling stage transistors are sized to generate the switched voltage efficiently, while the level-shifting stage transistors are sized for stable signal conversion. This asymmetric design optimizes switching speed while maintaining performance consistency across process variations.
Data Source
AI summary
An improved level shifter for use in integrated circuits is disclosed. The level shifter is able to achieve a switching time below 1 ns while still using the core power supply voltages, VDDL and VDDH, used in the prior art. The improved level shifter comprises a coupling stage and a level-switching stage.