Coupled Substrate Package Layout for Higher Memory Density

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Solution Overview

Problem

Conventional semiconductor device packages with 15 mm and 25 mm form factors face limitations in storage capacity while maintaining power and performance benefits, requiring an increase in storage density without compromising cooling requirements or adhering to industry-standard form factors.

Innovation Solution

A semiconductor device package design featuring multiple substrates, where additional substrates are oriented perpendicular to a primary substrate and housed within a specific enclosure, allowing for increased storage capacity by positioning more semiconductor dies within the same form factor dimensions, with a heat sink and thermally conductive layers for efficient cooling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional 5.9 mm and 9.5 mm form factor packages are used, then the number of packages per server rack increases, but the power and performance per package decreases and cooling requirements increase

Engineering Contradiction:
Improvenumber of packages per server rackVSAvoidpower and performance per package
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent transitions from a conventional planar substrate layout to a three-dimensional configuration by adding a second substrate oriented perpendicular to the first substrate. This vertical stacking approach increases storage capacity per package while maintaining the 15 mm or 25 mm form factor dimensions, thereby improving power and performance per package without increasing the number of packages required per server rack.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Use of energy by moving object

If 15 mm and 25 mm form factor packages are used, then power and performance per package improves, but the storage capacity per package is limited by form factor dimensions

Engineering Contradiction:
Improvepower and performance per packageVSAvoidstorage capacity per package
Core Design Contradiction:
Use of energy by moving objectVSQuantity of substance

Solution Approach 1:

The patent implements a nested configuration where a second substrate is positioned within the vertical space above the first substrate, both housed within the same 15 mm or 25 mm form factor enclosure. This nesting strategy effectively doubles the storage capacity per package while maintaining the same external dimensions and preserving the power and performance benefits of the larger form factor packages.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Quantity of substance

If additional substrates are added to increase storage capacity, then storage density increases, but cooling requirements and thermal management become more complex

Engineering Contradiction:
Improvestorage capacity per packageVSAvoidcooling requirements
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent applies different thermal management approaches to different regions of the package. The first substrate and second substrate are positioned to utilize available vertical space, with each substrate potentially having its own thermal management characteristics. This localized approach allows for efficient heat dissipation from each substrate independently, managing thermal loads effectively despite the increased storage density.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances storage capacity by at least 150% to 350% compared to conventional packages of the same form factor, while maintaining power and performance benefits and reducing cooling requirements, by strategically positioning additional substrates and semiconductor dies within the package.

Implementation Method 1

with a heat sink and thermally conductive layers for efficient cooling

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240203851A1Semiconductor Device Package with Coupled Substrates
Publication Date: 2024.06.20 SANDISK TECHNOLOGIES LLC
  • US20240203851A1 patent drawing
  • US20240203851A1 patent drawing
  • US20240203851A1 patent drawing

AI summary

A semiconductor device package includes a first substrate and receiving ports electrically connected to the first substrate. First semiconductor dies are electrically connected to and mounted directly on the first substrate. A second substrate is electrically connected to the first substrate via a corresponding receiving port and is oriented generally perpendicular to the first substrate. Second semiconductor dies are electrically connected to and mounted directly on the second substrate. A housing substantially encloses each of the above mentioned components. The receiving ports allow for additional substrates carrying semiconductor memory dies to be connected to the first substrate thereby increasing the total storage capacity of the semiconductor device package while conforming to a predefined form factor.