Functional Coverage Synthesis for Hardware Emulation
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Solution Overview
Problem
Current methods for functional coverage in hardware emulation and formal verification face challenges due to memory limitations and time-consuming processes, leading to hardware capacity overhead and inefficient synthesis of counters and bin indicator circuits.
Innovation Solution
The approach optimizes the synthesis of functional coverage by converting the definition of functional coverage into a form that reduces the number of logic gates and computer resources required, avoiding unnecessary bin indicator circuits and using interval tree logic to merge adjacent ranges, and employing hyperrectangular representation for cross bins to reduce capacity overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If many counters are synthesized in hardware for functional coverage, then coverage measurement capability is improved, but hardware capacity overhead increases
Solution Approach 1:
The patent merges multiple bin indicator circuits by identifying and combining logic gates that compute identical or overlapping bin conditions. Instead of synthesizing separate counters for each bin, the method consolidates common logic pathways, thereby reducing the total number of hardware resources required while maintaining the ability to measure coverage across all bins.
Solution Approach 2:
The patent extracts and eliminates unnecessary bin indicator circuits through formal verification analysis. By determining which bins are unreachable or redundant based on the design specification, the method removes the corresponding hardware circuits from the synthesis, reducing hardware capacity overhead while preserving measurement capability for essential coverage bins.
2Ease of manufacture
If straightforward synthesis algorithms are used for functional coverage, then implementation simplicity is maintained, but compilation time increases due to large volume of intermediate data
Solution Approach 1:
The patent performs preliminary analysis using formal verification to identify unreachable and redundant bins before the synthesis process begins. This preliminary action eliminates unnecessary intermediate data generation during synthesis, significantly reducing compilation time while maintaining implementation simplicity for the essential coverage bins.
3Reliability
If formal verification is run to check coverage attainability, then verification accuracy is improved, but execution time increases
Solution Approach 1:
The patent extracts only the essential and reachable bins from the full set of coverage bins through formal verification analysis. By focusing verification efforts on only those bins that can actually be reached in normal operation, the method maintains high verification accuracy while significantly reducing execution time compared to verifying all possible bins.
Data Source
AI summary
Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.