3D Memory Array Covered Void-Space for Via Isolation
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with direct electrical coupling to conductor tiers without alternative processing, and in achieving reliable electrical isolation between memory blocks.
Innovation Solution
The method involves forming a stack with vertically-alternating insulative and conductive tiers, creating channel openings that extend to the conductor tier for direct electrical coupling, and using conductive vias with insulating material to form a covered void-space around them, which allows for efficient electrical access and isolation between memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically-stacked memory cells are formed with direct electrical coupling to conductor tiers, then electrical access efficiency is improved, but manufacturing complexity increases due to alternative processing requirements
Solution Approach 1:
Conductive vias are formed within channel openings that extend through insulative tiers to conductor tiers, creating a nested structure where the via is embedded in the channel opening. This nesting allows direct electrical coupling without alternative processing, resolving the contradiction between improved electrical access efficiency and manufacturing complexity
Solution Approach 2:
Insulating material is introduced as an intermediary substance within channel openings to provide electrical isolation between adjacent conductive vias while allowing the vias to directly couple to conductor tiers. This mediator enables efficient electrical access while maintaining manufacturability through standard isolation techniques
2Reliability
If conductive vias are formed in channel openings to directly couple to conductor tiers, then electrical coupling reliability is improved, but process complexity increases
Solution Approach 1:
Channel openings are formed extending through insulative tiers to conductor tiers before conductive vias are deposited. This preliminary formation of the opening structure establishes reliable electrical coupling pathways in advance, reducing process complexity by following a logical sequence of operations
Solution Approach 2:
The channel openings serve dual purposes: they provide the structural pathway for conductive vias to reach conductor tiers, and they contain the insulating material that isolates adjacent vias. This self-service approach reduces process complexity by combining multiple functions into a single structural element
3Reliability
If insulating material is used to isolate conductive vias, then electrical isolation between memory blocks is improved, but manufacturing steps increase
Solution Approach 1:
The formation of insulating material within channel openings is combined with the via formation process. The insulating material is deposited and patterned as part of the same manufacturing sequence that creates the conductive vias, merging isolation and connection steps into a unified process that improves electrical isolation without significantly increasing manufacturing complexity
Data Source
AI summary
A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.