Covergroup Network Analysis for Verification Coverage
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Solution Overview
Problem
Traditional design verification techniques rely heavily on intuition for targeting uncovered or lightly covered coverpoints and coverage crosses in covergroups, making the process of achieving coverage closure inefficient and labor-intensive for verification engineers.
Innovation Solution
A computing system and toolset that performs functional verification on circuit designs to determine occurrences of coverpoints and coverage crosses, generating graphical presentations and rankings to identify and focus on under-covered areas, thereby guiding the generation of new test vectors for improved coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verification engineers use traditional intuition-based methods to identify uncovered coverpoints and coverage crosses, then the process relies on engineer expertise, but the productivity and efficiency of achieving coverage closure deteriorates due to the labor-intensive and time-consuming nature of the process
Solution Approach 1:
The patent introduces an intermediary system comprising a covergroup network analyzer and visualizer that acts as a mediator between the verification engine and the engineer. This intermediary automatically analyzes covergroup coverage data, identifies uncovered and lightly covered coverpoints and coverage crosses, and presents them in a visual format, thereby eliminating the need for engineers to manually analyze coverage data and significantly improving productivity while maintaining measurement precision
Solution Approach 2:
The verification system performs self-service by automatically generating coverage reports and identifying uncovered areas without requiring manual engineer intervention. The system autonomously processes coverage data, ranks coverpoints and coverage crosses by coverage percentage, and highlights critical areas needing attention, allowing the verification process to serve itself and reducing the burden on engineers
2Reliability
If verification engineers manually analyze all coverpoints and coverage crosses to achieve coverage closure, then comprehensive coverage can be achieved, but the loss of time and labor resources increases significantly
Solution Approach 1:
The patent applies local quality by differentiating between various levels of coverage (uncovered, lightly covered, adequately covered) and treating different coverpoints and coverage crosses differently based on their specific coverage status. The system prioritizes analysis and reporting on uncovered and lightly covered items while summarizing adequately covered items, allowing engineers to focus time and resources on critical areas rather than uniformly analyzing all coverpoints, thus reducing time loss while maintaining coverage completeness
Solution Approach 2:
The system implements feedback by continuously monitoring coverage metrics and providing real-time information about uncovered and lightly covered coverpoints and coverage crosses. This feedback loop allows engineers to make informed decisions about which areas to address next, preventing wasted time on already adequately covered items and ensuring comprehensive coverage is achieved efficiently through iterative improvement
Data Source
AI summary
This application discloses performing functional verification on a circuit design describing an electronic device and a computing system to determine occurrences of coverpoints and coverage crosses within a covergroup based on the results of the functional verification of the circuit design. Each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification. Each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently. The computing system can generate a graphical presentation of the covergroup. The graphical presentation include nodes, each of which corresponding to the coverpoints or the coverage crosses. The nodes can be arranged in the graphical presentation based on connectivity between the coverpoints and the coverage crosses and clustered in the graphical presentation based on the occurrences of the coverpoints and coverage crosses during the functional verification of the circuit design.