Covering Liner Structure for Void-Free Low-Capacitance Interconnects
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues with parasitic capacitance and void formation during the fabrication process.
Innovation Solution
A semiconductor device design featuring a porous insulating layer and covering liners with specific thickness and porosity, formed through a method involving sacrificial structures, supporting liners, and energy-removable layers, which reduces parasitic capacitance and enables void-free conductive feature formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication processes are used for scaling down semiconductor devices, then device density increases, but parasitic capacitance increases and void formation occurs
Solution Approach 1:
The patent introduces a porous liner material with controlled porosity (e.g., 30-70%) that is conformally deposited on conductive features. The porous structure reduces the dielectric constant of the liner, thereby reducing parasitic capacitance between adjacent conductive features while maintaining the required mechanical support and coverage during fabrication processes.
Solution Approach 2:
The patent employs a composite liner structure consisting of multiple layers including a first liner material (e.g., silicon nitride or silicon oxide) and a second porous liner material. This composite approach combines the advantages of different materials: the first layer provides mechanical strength and adhesion, while the porous second layer reduces parasitic capacitance, achieving both structural integrity and electrical performance.
2Ease of manufacture
If conventional liner structures are used, then fabrication is simpler, but voids form in conductive features during processing
Solution Approach 1:
The patent applies a porous liner conformally on the conductive features before subsequent fabrication steps. This preliminary action of depositing the porous liner provides mechanical support and prevents void formation during later processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), ensuring complete and uniform filling of conductive features without voids while maintaining ease of manufacture through standard deposition techniques.
3Manufacturing precision
If liner thickness is increased to prevent voids, then void-free conductive features are achieved, but parasitic capacitance increases
Solution Approach 1:
The patent utilizes porous liner materials that provide adequate mechanical support and void prevention even at reduced thicknesses (e.g., 5-50 nm). The porous structure maintains the necessary mechanical integrity to prevent void formation during fabrication while the reduced material density and lower dielectric constant significantly reduce parasitic capacitance compared to conventional dense liners of the same thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces parasitic capacitance and improves yield by forming conductive features without voids, enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
a porous insulating layer positioned above the substrate... a porosity of the porous insulating layer is between about 10% and about 50%
Implementation Method 2
applying an energy source to turn the energy-removable layer into a porous insulating layer... the energy-removable layer includes a base material and a decomposable porogen material
Data Source
AI summary
The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.