Covert Gates for Semiconductor IP Protection
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Solution Overview
Problem
Existing IC camouflaging techniques are vulnerable to reverse engineering attacks, leading to potential intellectual property infringement and hardware Trojan insertion, as they incur significant area, power, and delay overheads, and are susceptible to SAT and test-based attacks.
Innovation Solution
The introduction of 'covert gates' that appear indistinguishable from regular gates under SEM imaging, utilizing doping modifications and dummy inputs to mislead attackers, with minimal overhead and enhanced resistance to invasive and non-invasive attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional IC camouflaging techniques are used to protect logic gates, then the ability to identify logic gates is disrupted, but the design becomes vulnerable to SAT and test-based attacks and incurs significant area and performance overhead
Solution Approach 1:
Instead of making gates unidentifiable through complex camouflaging structures, the patent inverts the approach by making all gates appear identical through doping modifications. The covert gates are designed to look exactly like regular gates under SEM imaging, but with altered doping profiles that cause them to fail under SAT and test-based attacks, thereby protecting IP without adding area overhead.
Solution Approach 2:
The patent changes the doping parameters (concentration, depth, distribution) of transistors in covert gates to alter their electrical characteristics. By modifying doping profiles, the gates maintain identical physical appearance under imaging but exhibit different electrical behavior under attack conditions, achieving protection without structural complexity.
2Difficulty of detecting and measuring
If camouflaged gates with dummy contacts are used to disrupt gate identification, then some gates become ambiguous in the netlist, but the technique is vulnerable to attacks adapted from VLSI testing and Boolean satisfiability
Solution Approach 1:
Rather than trying to make gates unidentifiable (which creates vulnerability), the patent inverts the approach by making gates appear perfectly identifiable as regular gates, while the doping modifications cause them to fail under attack conditions. This reverses the vulnerability model from structural analysis to electrical behavior analysis.
Solution Approach 2:
The patent creates a composite transistor structure with multiple doping regions (light doping, heavy doping, dual doping) within the same physical footprint. This composite doping profile gives the gate identical appearance to regular gates but fundamentally different electrical characteristics that resist SAT and test-based attacks.
3Area of stationary object
If covert gates with doping modifications are used to maintain indistinguishability from regular gates, then area overhead is minimized, but fabrication complexity increases
Solution Approach 1:
The patent achieves covert gate functionality by changing doping parameters (concentration, depth, distribution) rather than adding physical structures. These parameter changes can be implemented using standard semiconductor fabrication processes like ion implantation and diffusion, maintaining compatibility with existing manufacturing while achieving the desired electrical characteristics.
Solution Approach 2:
The same fabrication infrastructure and doping processes used for regular transistor manufacturing are leveraged to create covert gates. The doping modifications can be integrated into existing process flows, allowing the same factory to produce both regular and covert gates without requiring specialized equipment or processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Covert gates significantly increase attack complexity by making all gates in the design appear suspect, reducing the effectiveness of SAT and test-based attacks, while maintaining minimal area, power, and delay overheads, thus providing robust protection for semiconductor intellectual property.
Implementation Method 1
The always-on PMOS transistor comprises: an active region comprising first dopants at a first carrier concentration under a gate of the always-on PMOS transistor; a source and a drain comprising second dopants; and a layer of third dopants at a third carrier concentration arranged inside the active region, wherein the third carrier concentration of the third dopants is higher than the first carrier concentration of the first dopants, such that the always-on PMOS transistor remains in an always-on state
Implementation Method 2
a layer of dielectric material coated on a side wall and a bottom of the contact hole to insulate said gate from a conductive material filled into the contact hole, such that the always-off NMOS transistor remains in an always-off state
Data Source
AI summary
Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. The cell camouflaging covert gate leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. A comprehensive security analysis of the covert gate shows that it achieves high resiliency against SAT and test-based attacks at very low overheads. Models are derived to characterize the covert cells, and metrics are developed to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.