Chip-on-Wafer Assembly Warpage Mitigation via Back-Side Metallization
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Solution Overview
Problem
The challenge in electronic packaging is the occurrence of warping during the reflow process in chip-on-wafer assemblies, leading to non-contact or separation between the chip and substrate, which affects product yield due to factors like size, chip height uniformity, and thermal expansion.
Innovation Solution
A method involving a two-step molding process with underfill and over-molding, followed by substrate thinning and back side metallization, and the use of a plate with adhesive to mitigate warpage, ensuring proper encapsulation and structural support of dies and micro-bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a chip-on-wafer assembly undergoes reflow process, then bonding between chip and substrate is achieved, but warping occurs causing non-contact or separation
Solution Approach 1:
The patent applies preliminary anti-action by performing underfill dispensing before the reflow process. The underfill material is dispensed into the gaps between the chip and substrate, creating a supportive structure that counteracts the warping forces that will occur during subsequent reflow processing, thereby preventing separation while maintaining bonding reliability
Solution Approach 2:
The patent implements preliminary action by conducting the underfill dispensing operation prior to reflow. This preliminary step establishes a protective and supportive underfill structure that will mitigate warping effects during the upcoming reflow process, ensuring that the chip remains in contact with the substrate throughout heating and cooling cycles
2Ease of manufacture
If molding material and chips have different thermal expansion coefficients, then assembly is formed, but warpage and warping uniformity are affected
Solution Approach 1:
The patent applies parameter changes by carefully selecting and controlling the thermal expansion coefficient of the molding material to match that of the chip and substrate assembly. This parameter matching reduces differential thermal stress during temperature cycling, thereby minimizing warpage and improving warping uniformity while maintaining ease of assembly formation
3Length of moving object
If wafer thinning is performed, then package thickness is reduced, but structural support is compromised
Solution Approach 1:
The patent employs composite materials by combining the thinned wafer substrate with the underfill material and molding compound to create a composite structure. The underfill and molding materials provide additional structural support that compensates for the reduced thickness of the wafer, maintaining overall strength while achieving the desired thin package profile
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warpage and ensures reliable contact between the chip and substrate, enhancing product yield by maintaining structural integrity and uniformity throughout the manufacturing process.
Implementation Method 1
a plate (160) attached over a first side of the CoW assembly, wherein the plate (160) is attached by an adhesive (162) uniformly applied for bonding the plate (160) and the CoW assembly
Data Source
AI summary
A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.