CoWoS Edge-Pad Memory Stack for TSV-Free Thermal Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 2.5D/3D ICs face challenges in power, performance, area, and cost optimization due to constraints from bottom/top electrical interconnects, particularly in forming through-silicon vias and aligning semiconductor dies, and suffer from inadequate heat dissipation due to low thermal conductivity materials like silicon dioxide, exacerbated by stacked DRAM memory dies.
Innovation Solution
The IC structure incorporates edge-pad semiconductor dies with high thermal conductivity materials like SiC, BN, AlN, W, or copper between and around semiconductor dies, eliminating through-silicon vias and using redistribution layers for signal and power distribution, along with heat dissipation layers to manage thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias are used for electrical interconnects in stacked semiconductor dies, then electrical connectivity between dies is achieved, but manufacturing complexity and alignment precision requirements increase significantly
Solution Approach 1:
The patent extracts the electrical interconnect function from the traditional through-silicon via approach by implementing edge pads on the sidewalls of semiconductor dies. This allows electrical connections to be made at the edges of the dies rather than requiring complex through-silicon via formation and alignment, thereby reducing manufacturing complexity while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from planar electrical interconnects (top/bottom surfaces) to three-dimensional edge-based interconnects by placing pads on the sidewalls of semiconductor dies. This dimensional change enables connections without requiring precise through-silicon via alignment, as the edge pads can be bonded to corresponding pads on adjacent dies in a more tolerant configuration.
2Reliability
If traditional silicon dioxide insulation layers are used in stacked semiconductor dies, then electrical insulation is provided, but thermal conductivity is insufficient leading to heat dissipation problems
Solution Approach 1:
The patent employs composite material structures by combining silicon dioxide insulation layers with high thermal conductivity materials such as boron nitride (BN) or aluminum nitride (AlN). This composite approach maintains the electrical insulation properties of silicon dioxide while incorporating materials with superior thermal conductivity to enable effective heat dissipation from the stacked semiconductor dies.
3Productivity
If multiple DRAM memory dies are vertically stacked to increase integration density, then storage capacity is improved, but heat dissipation capability deteriorates due to low thermal conductivity materials
Solution Approach 1:
The patent uses composite material structures by combining silicon dioxide insulation layers with high thermal conductivity materials such as boron nitride (BN) or aluminum nitride (AlN). This composite approach maintains the electrical insulation properties of silicon dioxide while incorporating materials with superior thermal conductivity to enable effective heat dissipation from the stacked semiconductor dies.
Solution Approach 2:
The patent introduces high thermal conductivity materials as intermediary layers between stacked semiconductor dies. These intermediary layers act as thermal pathways that conduct heat away from the dies, preventing heat accumulation while maintaining the electrical insulation function, thus enabling better thermal management in high-density stacked configurations.
4Manufacturing precision
If edge pads are arranged on sidewalls of semiconductor dies instead of traditional top/bottom surfaces, then electrical interconnect alignment is simplified, but manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar electrical interconnects (top/bottom surfaces) to three-dimensional edge-based interconnects by placing pads on the sidewalls of semiconductor dies. This dimensional change enables connections without requiring precise through-silicon via alignment, as the edge pads can be bonded to corresponding pads on adjacent dies in a more tolerant configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances thermal management and electrical connectivity, optimizing power, performance, and reducing costs by improving heat dissipation and electrical interconnect efficiency in 2.5D/3D ICs.
Implementation Method 1
The IC structure incorporates edge-pad semiconductor dies with high thermal conductivity materials like SiC, BN, AlN, W, or copper between and around semiconductor dies
Data Source
AI summary
An IC structure includes a memory stack, which includes a plurality of semiconductor dies horizontally separate with each other, a memory controller chip, an interposer, a logic processor chip and a packaging substrate. Each semiconductor die includes a top surface, a bottom surface, and four sidewalls, and a plurality of edge pads are arranged along the first sidewall. The memory controller chip is disposed under and electrically connected to the plurality of edge pads of each semiconductor die, wherein the first sidewall of each semiconductor die faces the memory controller chip. The interposer is disposed under and electrically connected to the memory controller chip. The logic processor chip is electrically connected to the memory controller chip. The packaging substrate is disposed under and electrically connected to the interposer.