CoWoS Package Heat Spreader Ring for Thermal Stress Relief

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Solution Overview

Problem

The semiconductor industry faces challenges in bonding integrated circuit chips directly onto substrates due to increased integration density and thermal expansion issues in 3D packaging, leading to reliability concerns and TIM degradation.

Innovation Solution

The implementation of a chip-on-wafer-on-substrate (CoWoS) package with a heat spreader having concave portions and a ring with different thermal expansion coefficients, which reduces stress and enhances heat dissipation by increasing the TIM coverage area and using underfill materials to reduce delamination risks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but the area occupied by the integrated circuit decreases making direct bonding difficult

Engineering Contradiction:
Improveintegration densityVSAvoidchip area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from 2D planar integration to 3D vertical stacking by introducing an interposer layer between the chip and substrate. This allows multiple chips to be stacked vertically, increasing integration density without further reducing chip area, and enables direct bonding of smaller high-density chips to the interposer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer serves as an intermediary component between the integrated circuit chip and the substrate. It redistributes ball contact areas from the chip to a larger area, enabling bonding of high-density chips that would otherwise be too small to bond directly to the substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If 3D packaging is implemented with multiple chips, then integration density increases, but thermal expansion issues and reliability concerns worsen

Engineering Contradiction:
Improveintegration densityVSAvoidpackage reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent changes the physical parameters of the packaging structure by introducing an interposer with specific material properties and a redesigned lid structure with increased volume and modified geometry. These parameter changes accommodate thermal expansion differences in 3D packaging, reducing stress and improving reliability.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If chip size is reduced for higher integration density, then more components fit in given area, but ability to bond chip directly onto substrate deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidbonding capability
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The interposer acts as a mediator that accepts bonds from small, high-density chips on one side and provides a larger bonding area on the other side for substrate connection. This intermediary structure enables bonding of chips that are too small for direct substrate bonding.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent moves from 2D direct bonding to 3D indirect bonding through the interposer, allowing small chips to be bonded to the interposer in one dimension while the interposer provides the necessary bonding area in another dimension for substrate connection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution improves device reliability by minimizing thermal expansion issues, increasing heat dissipation, and reducing the risk of delamination between semiconductor chips and underfill materials.

Implementation Method 1

a thermal interface material (TIM) is applied to a top surface of the package component

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

reduced expansion and contraction of the lid during subsequent high temperature processes

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20230411234A1Integrated circuit packages and methods of forming the same
Publication Date: 2023.12.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230411234A1 patent drawing
  • US20230411234A1 patent drawing
  • US20230411234A1 patent drawing

AI summary

A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, wherein the ring surrounds the first die and the interposer; and a heat spreader over and coupled to the ring and the first die, wherein a first coefficient of thermal expansion of a first material of the ring and a second coefficient of thermal expansion of a second material of the heat spreader are different, and wherein in a cross-sectional view a combined structure of the heat spreader and the ring have a H-shaped profile.