CoWoS Interposer Grooving to Prevent Sawing Damage
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Solution Overview
Problem
Current Chip-on-Wafer-on-Substrate (CoWoS) package structures face challenges in the packaging process, particularly in preventing damage to the interconnect structure during pre-cut and sawing processes, which can lead to cracking or chipping issues.
Innovation Solution
The process involves forming intersected grooves on the interposer wafer through non-contact pre-cut processes like laser grooving and subsequent wafer dicing, followed by a wafer sawing process, where the grooves are designed to keep the interconnect structure away from the cutting blades, thereby preventing direct contact and potential damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-cut and sawing processes are performed on CoWoS package structures, then the packaging process can be completed and productivity improved, but the interconnect structure may be damaged causing cracking or chipping
Solution Approach 1:
The method performs preliminary grooving actions before the main sawing process. Intersected grooves are formed on the interposer wafer prior to sawing, creating predetermined separation lines that guide the sawing process and prevent uncontrolled cracking that would otherwise damage the interconnect structure during cutting
Solution Approach 2:
The interposer wafer is divided into multiple sections through intersected grooves that segment the structure along predetermined paths. This segmentation allows the wafer to be separated into individual packages without forcing the sawing blade through the fragile interconnect structure, thereby maintaining its integrity while still achieving the desired segmentation for productivity
2Ease of manufacture
If conventional sawing processes are used on CoWoS packages, then manufacturing can proceed, but cracking and chipping of the interconnect structure occurs
Solution Approach 1:
The grooving process is performed as a preliminary step before sawing, creating predetermined separation lines on the interposer wafer. This preliminary action establishes safe cutting paths that guide subsequent sawing operations, ensuring that the sawing blade follows predetermined grooves rather than forcing through the interconnect structure, thereby maintaining manufacturing precision without complicating the overall manufacturing process
Solution Approach 2:
The intersected grooves act as an intermediary element between the sawing process and the interconnect structure. The grooves provide a predetermined separation path that mediates the interaction between the sawing blade and the fragile interconnect structure, allowing the blade to cut along the grooves rather than directly contacting and damaging the interconnect structure, thus preserving manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents cracking or chipping of the interconnect structure during the packaging process, ensuring the integrity of the CoWoS package structures and improving yield and reliability.
Implementation Method 1
forming intersected grooves on an interposer wafer through non-contact pre-cut processes like laser grooving
Data Source
AI summary
A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.