CoWoS Microbump Testing via Standardized Structures
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Solution Overview
Problem
Current methods for testing chip-on-wafer connections in CoWoS packages are either unreliable and time-consuming, such as physical examination, or costly and non-standardized, like product chip probing, due to the need for manual inspection and chip-specific testing probes.
Innovation Solution
Incorporating standardized test structures in pre-selected areas of the top die, allowing for universal electrical testing of microbump connections using a standardized testing probe card, which reduces human error and testing time while enabling reliable connection quality assessment without rerouting active circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical examination is used to test CoW connections, then connection quality can be visually inspected, but the testing process becomes time-consuming and unreliable due to manual inspection limitations
Solution Approach 1:
The patent replaces manual physical examination with automated electrical testing using standardized test structures and probe cards. Electrical measurements objectively detect connection quality without human intervention, eliminating the time-consuming and error-prone manual inspection process while maintaining or improving detection accuracy.
Solution Approach 2:
The patent uses standardized test structures that are replicated across multiple chips and wafers. These test structures serve as copies or proxies for the actual product connections, allowing automated electrical testing to assess connection quality without examining every physical connection manually.
2Reliability
If product chip probing is used to test CoW connections, then electrical connection testing is more reliable, but the cost increases due to chip-specific testing probe requirements
Solution Approach 1:
The patent introduces standardized test structures with standardized probe card interfaces that can be used across different chip designs and layouts. This universal testing approach eliminates the need for custom chip-specific probe cards, reducing testing costs while maintaining reliable electrical connection testing through standardized measurement procedures.
3Reliability
If product chip probing is used to test CoW connections, then electrical connections can be functionally tested, but the process becomes non-standardized due to chip layout dependencies
Solution Approach 1:
The standardized test structures are designed with fixed geometries and electrical characteristics that are independent of the surrounding product circuitry. The same standardized probe card can test connections across different chip layouts without modification, achieving both reliable electrical testing and standardization across diverse chip designs.
Solution Approach 2:
The patent separates the testing function from the product circuitry by using dedicated standardized test structures. These test structures are distinct segments that can be tested independently using standardized procedures, allowing reliable electrical testing without being constrained by varying product chip layouts.
Data Source
AI summary
An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.