CoWoS Interconnect Package Testing for Accurate LSI Placement
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Solution Overview
Problem
The challenge in chip-on-wafer-on-substrate (CoWoS) packaging is the potential for leakage issues due to incorrect placement of local silicon interconnect dies (LSIs), leading to reduced yield and increased costs, as well as the need for effective verification testing of 3D packaging structures.
Innovation Solution
Incorporation of test circuits in the redistribution structures for probing and electrical testing to confirm correct placement of LSIs, along with the use of test structures and probe cards for intermediate and final verification, ensuring accurate positioning and reducing waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If test circuits are incorporated into redistribution structures for probing and electrical testing, then manufacturing precision and reliability are improved through verification of LSI placement, but device complexity increases due to additional test structures and probing procedures
Solution Approach 1:
Test circuits are incorporated into the redistribution structure before LSI placement, and test structures are formed in advance to enable verification testing. This preliminary action allows placement accuracy to be confirmed before final assembly, preventing incorrect LSI placement without requiring complex post-assembly inspection equipment
Solution Approach 2:
Test circuits and test structures serve as intermediary elements between the LSI placement process and final verification. These intermediate test structures enable indirect measurement of placement accuracy through electrical testing, simplifying the overall verification process while maintaining high precision
2Reliability
If verification testing is performed to confirm correct placement of LSIs, then production yield is improved by reducing defects, but productivity decreases due to additional testing time and process steps
Solution Approach 1:
The redistribution structure performs self-verification through integrated test circuits that automatically detect placement errors. The structure tests itself without requiring external inspection equipment or manual verification, thereby improving yield while minimizing additional process steps and maintaining productivity
Solution Approach 2:
Test circuits provide immediate feedback on LSI placement accuracy through electrical measurements. This real-time feedback allows for in-process correction or rejection of defective placements, improving overall yield while enabling rapid verification that does not significantly impact manufacturing throughput
Data Source
AI summary
The present disclosure relates to a package. The package comprises an interconnect die, an encapsulant, a first redistribution structure and an integrated circuit die. The interconnect die comprises a semiconductor substrate and an interconnect structure. The interconnect structure is disposed over the semiconductor substrate and comprising a first test circuit. The encapsulant surrounds the interconnect die. The first redistribution structure is disposed over the interconnect die and the encapsulant. The first redistribution structure comprises a second test circuit, a first test structure, a second test structure and bonding structures. The second test circuit is connected with the first test circuit. The first test structure and the second test structure are connected with the second test circuit. The integrated circuit die is electrically connected to the bonding structures and separated from the first test structure and the second test structure.