CoWP Bottom Electrode for Resistive Memory
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Solution Overview
Problem
In the development of resistive memory devices, particularly for sub-14 nm technology nodes, the challenge lies in forming a bottom electrode that is thin enough to fit within shrinking spaces while protecting interconnect layers from degradation during patterning, etching, and film growth, and existing methods require additional lithography mask levels and etching steps, increasing fabrication costs and degrading yield.
Innovation Solution
A shallow bottom electrode structure is formed using electroless deposition of cobalt tungsten phosphorus (CoWP) on exposed interconnect layers, which are approximately 10-20 nm thick, eliminating the need for additional mask levels and etching steps, and optimizing the electrochemistry of the deposition process to align with the MTJ or RRAM device requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bottom electrode thickness is increased to protect interconnect layers from degradation during patterning, etching, and film growth, then the protection capability is improved, but the device fits within shrinking spaces becomes worse
Solution Approach 1:
The patent changes the material composition parameters of the bottom electrode by incorporating multiple materials (tungsten, cobalt, platinum) in specific ratios, and optimizes deposition parameters (temperature, pressure, deposition rate) to achieve a thin electrode structure (10-20 nm) that provides adequate protection while fitting sub-14 nm technology nodes
Solution Approach 2:
The patent uses composite material structures for the bottom electrode, combining tungsten, cobalt, and platinum in specific configurations. This composite approach allows the thin electrode to provide enhanced protection capability through synergistic material properties while maintaining the required thin profile for sub-14 nm processes
2Reliability
If conventional methods are used to form bottom electrodes, then the protection function is achieved, but additional lithography mask levels and etching steps are required, increasing fabrication cost and degrading yield
Solution Approach 1:
The patent merges the bottom electrode formation process with the interconnect layer deposition process. The bottom electrode materials are deposited simultaneously with or immediately adjacent to the interconnect layers in the same deposition chamber, eliminating the need for separate lithography mask levels and etching steps that would otherwise be required
Solution Approach 2:
The deposition process serves multiple functions: it forms the interconnect layers, creates the bottom electrode structure, and provides protection for subsequent MTJ or RRAM device formation. This multi-functional approach reduces the overall number of fabrication steps while achieving the required protection function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of thin bottom electrodes that protect interconnect layers from degradation, supports sub-14 nm processes, and reduces fabrication costs by eliminating the need for additional processing steps and mask levels, thereby improving yield and efficiency.
Implementation Method 1
Bottom electrodes may be formed on top of the exposed interconnects using electroless deposition
Data Source
AI summary
A method includes patterning a photo resist layer on top of a semiconductor device. The semiconductor device includes a lower portion, a capping layer formed on top of the lower portion, and an optional oxide layer formed on top of the capping layer. The lower portion includes a dielectric material and an interconnect. The method also includes etching portions of the semiconductor device based on the photo resist layer to expose the interconnect. The method further includes depositing a bottom electrode of a resistive memory device on the interconnect. The bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).