CPC Circular Buffer Concurrent Bit Location for HARQ Speed
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Solution Overview
Problem
Current 3GPP CPC systems face inefficiencies in HARQ processing speed due to the lack of concurrent location and processing of systematic and parity bits in physical channel memory, which hampers high-speed packet-switched data transmission in WCDMA mobile wireless systems.
Innovation Solution
A method and system that concurrently locate and process systematic and parity bits in physical channel memory using a CPC circular buffer, allowing for simultaneous computation and storage of memory locations based on transmission parameters, enabling faster HARQ processing by performing rate matching on these bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If systematic bits and parity bits are processed sequentially in physical channel memory, then the processing logic is simple, but the HARQ processing speed is reduced
Solution Approach 1:
The patent segments the physical channel memory into distinct regions for systematic bits and parity bits, with separate pointers (systematic bit pointer and parity bit pointer) for each type. This segmentation enables concurrent access and processing of both bit types simultaneously, resolving the contradiction by allowing parallel operations while maintaining organized, manageable memory structures.
Solution Approach 2:
The patent introduces a temporal dimension to the processing by enabling simultaneous computation of memory locations for both systematic and parity bits. Instead of sequential processing in a single dimension, the system computes and accesses both bit types concurrently in parallel, effectively adding a time dimension to the processing workflow and achieving faster HARQ processing.
2Loss of energy
If HS-SCCH signaling is used for control information transmission, then the control information can be reliably transmitted, but the signaling overhead increases and UE battery life decreases
Solution Approach 1:
The patent extracts the control information (HS-SCCH signaling) from the normal transmission protocol and handles it separately through pre-computation of memory locations. By taking out the control signaling function and implementing it through pre-calculated pointers and direct memory access, the system eliminates the need for continuous HS-SCCH transmissions, thereby reducing signaling overhead and UE energy consumption while maintaining reliable control information delivery.
Solution Approach 2:
The patent applies preliminary action by pre-computing the memory locations for systematic and parity bits before actual transmission. This pre-computation allows the UE to prepare the necessary control information and memory structures in advance, eliminating the need for subsequent HS-SCCH signaling during the transmission phase, thus conserving battery life while ensuring control information is already in place for reliable transmission.
Data Source
AI summary
A UE receives a HS-PDSCH transmission from a base station and concurrently performs rate matching on systematic bits and parity bits (parity 1 bits, parity 2 bits) of the received HS-PDSCH transmission. The systematic bits and parity bits are buffered in a CPC circular buffer to support HARQ processing in a HS-SCCH-less operation of the base station. Memory locations are computed for the systematic bits and the parity bits according to corresponding transmission parameters such as, for example, redundancy version, number of systematic bits and/or number of physical channels. The systematic bits and the parity bits are stored in the corresponding computed memory locations of the CPC circular buffer. At least a portion of the stored systematic bits and parity bits are concurrently generated based on corresponding transmission parameters from the CPC circular buffer per request to support concurrent rate matching on systematic bits and parity bits.