CPC Tile Twinax Interconnects for Low-Loss High-Density Routing
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Solution Overview
Problem
Current systems face challenges in achieving high-speed channel loss budgets and cost-effectiveness for connections between ASICs and PCBs due to lossy materials and routing techniques, especially with the development of faster SerDes interface speeds, and existing copper cable solutions have size and compatibility issues with co-packaged optics.
Innovation Solution
The implementation of a co-packaged cables (CPC) tile with a slot and channels for twinaxial cables, combined with preloaded elastomer pins, allows for direct and high-density electrical connections between optical or copper cables and ASICs/PCBs, reducing insertion loss, return loss, and crosstalk, while being compatible with existing co-packaged optics and requiring less mechanical force for termination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCB routing and ASIC escape are used to achieve high-speed connections, then connection speed can be increased, but channel loss increases and cost increases
Solution Approach 1:
The patent transitions from traditional PCB surface routing to a three-dimensional vertical routing architecture. Channels are drilled through the PCB substrate to create direct vertical pathways, eliminating the need for signal to traverse across lossy PCB surfaces. This dimensional change from 2D to 3D routing dramatically reduces channel loss while maintaining high-speed connectivity.
Solution Approach 2:
The invention extracts the cable connection interface directly from the PCB surface and integrates it into the PCB substrate itself. By drilling channels through the PCB and creating internal connection points, the patent removes the need for external ASIC escape routes and surface-mounted connectors, thereby reducing the lossy transmission path.
2Loss of energy
If copper cables are used to reduce loss budgets, then channel loss decreases, but interconnect density is low and placement near ASICs is difficult
Solution Approach 1:
The patent utilizes vertical drilling to create channels that pass through the PCB substrate, enabling high-density interconnects in the vertical dimension. Multiple channels can be packed closely together in the vertical direction without the spacing constraints of surface-mounted copper cables, thereby achieving both low loss and high density simultaneously.
Solution Approach 2:
The invention nests the cable connection channels directly within the PCB substrate structure. By integrating the channels into the PCB itself rather than mounting cables externally, the patent achieves compact, high-density interconnects that can be placed close to ASICs while maintaining low signal loss through direct routing.
3Reliability
If traditional cable termination methods are used, then connection can be established, but mechanical force required is high and manufacturing yield decreases
Solution Approach 1:
The patent incorporates pre-loaded elastomer pins within the PCB channels before cable installation. These elastomer pins are pre-compressed during PCB manufacturing to provide inherent contact pressure. When cables are inserted, the elastomer pins automatically engage with the cable conductors, eliminating the need for high mechanical force during termination and improving manufacturing yield.
Solution Approach 2:
The invention changes the mechanical properties of the termination interface by using elastomer materials with specific elastic properties. The elastomer pins can deform elastically to accommodate cable positioning variations while maintaining consistent contact pressure, thereby reducing the force required for termination and improving connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides superior electrical performance, higher connection density, cost-effectiveness, and flexibility, enabling better manufacturing yield and compatibility with existing components, while reducing the mechanical force required for cable termination and allowing for easier integration with co-packaged optics.
Implementation Method 1
a plurality of elastomer pins positioned in the plurality of channels
Data Source
AI summary
A communication interconnect system is described. The system may include a co-packaged cables (CPC) tile with a slot formed from a first surface to slot surface at a first depth in the CPC tile and a plurality of channels formed between the slot surface and a second surface opposite the first surface. The system may also include a twinaxial cable with a pair of conductors positioned in the slot such that the pair of conductors are inserted in a pair of channels of the plurality of channels to establish an electrical connection between the twinaxial cable and the pair of channels. The system also includes a plurality of elastomer pins positioned in the plurality of channels adjacent to the second surface.