CPLD Delay Circuit for Server Restart Signal Conflict
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Solution Overview
Problem
The trigger signal from a central processing unit (CPU) in a server can conflict with the system management of the platform controller hub (PCH) chip, preventing the server from restarting effectively when a serious error occurs.
Innovation Solution
A complex programmable logic device (CPLD) is electrically coupled between the CPU and the PCH chip, delaying the trigger signal for a preset time before sending it to the PCH chip, which comprises a sampling module, latching module, counting module, and processing module to process and output the signal, allowing the server to restart.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CPU directly outputs the trigger signal to the PCH chip, then the error response speed is fast, but the trigger signal conflicts with the PCH's system management and prevents server restart
Solution Approach 1:
The patent introduces a CPLD (Complex Programmable Logic Device) as an intermediary component between the CPU and PCH chip. The CPLD receives the trigger signal from the CPU, applies a delay treatment, and then outputs the delayed signal to the PCH chip. This intermediary device resolves the timing conflict between the CPU's error response signal and the PCH's system management operations, enabling reliable system restart while maintaining fast error response capability.
2Reliability
If the trigger signal is delayed before reaching the PCH chip, then the conflict with system management is avoided, but the error response time increases
Solution Approach 1:
The patent modifies the timing parameter of the trigger signal by introducing a controlled delay through the CPLD. The delay duration is precisely adjusted to match the system management timing requirements, transforming the signal timing characteristics to avoid conflict with PCH operations while maintaining the overall error response effectiveness.
3Reliability
If the trigger signal timing is adjusted to avoid conflict, then system restart is enabled, but the signal processing complexity increases
Solution Approach 1:
The CPLD serves as a dedicated intermediary device that encapsulates the timing adjustment logic. By offloading the signal processing complexity to this specialized component, the main CPU and PCH chip can operate with their original simple interfaces, achieving system restart capability without significantly increasing the overall system complexity.
Data Source
AI summary
An electronic device with reliable restart function includes a central processing unit (CPU), a complex programmable logic device (CPLD), and a platform controller hub (PCH). The CPU also outputs a trigger signal when a serious error occurs in the electronic device. The CPLD obtains the trigger signal from the CPU, and delays the trigger signal for a first preset time. The PCH chip obtains the trigger signal delayed by the CPLD, and controls the electronic device to perform a system restart according to the trigger signal.