CPLD Edge Detection and FIFO Buffer for Real-Time BMC Signal Monitoring
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Solution Overview
Problem
The existing communication method between the Baseboard Management Controller (BMC) and the Complex Programmable Logic Device (CPLD) using the I2C bus is not real-time and is slow in response, leading to potential loss of signal changes and increased resource occupation for the BMC.
Innovation Solution
The implementation of a data transmission module with a FIFO memory and an edge detection module in the CPLD, which allows for the storage and immediate transmission of signal changes to the BMC through the I2C bus, reducing the need for continuous polling and minimizing communication time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the BMC uses fixed interval polling to access the CPLD through I2C bus, then the communication method is simple to implement, but the response time is slow and real-time monitoring capability is poor
Solution Approach 1:
The CPLD proactively pushes data changes to the BMC through interrupt signals before the BMC needs to query them. The edge detection module detects signal changes and triggers interrupt requests, allowing the BMC to respond immediately to events without waiting for the next polling cycle, thus improving response speed without requiring complex continuous monitoring mechanisms
Solution Approach 2:
The system combines periodic polling with event-driven interrupts. The BMC continues to use periodic polling for normal operation, but when the CPLD detects signal changes through edge detection, it sends interrupt signals to trigger immediate BMC attention, effectively combining the simplicity of periodic action with the responsiveness of event-driven action
2Reliability
If the BMC continuously polls the CPLD for status updates, then real-time monitoring is achieved, but resource occupation of the BMC increases
Solution Approach 1:
The CPLD performs self-service by automatically detecting signal changes through its internal edge detection module and generating interrupt signals when changes occur. This eliminates the need for the BMC to continuously poll the CPLD, as the CPLD independently monitors its own inputs and notifies the BMC only when relevant changes occur, reducing BMC resource occupation while maintaining real-time monitoring capability
Solution Approach 2:
The system implements feedback through interrupt signals that provide information about signal changes from the CPLD to the BMC. Instead of the BMC continuously asking for status updates, the CPLD provides feedback about changes autonomously, allowing the BMC to adjust its resource usage by only processing interrupts when actual changes occur rather than continuously polling
3Loss of information
If the BMC uses fixed interval polling to access the CPLD, then the communication protocol is simple, but signal changes may be lost between polling intervals
Solution Approach 1:
The CPLD performs preliminary detection of signal changes using the edge detection module and stores change information in internal registers before the BMC needs to read them. When an interrupt is triggered, the CPLD has already captured and prepared the signal change data, ensuring no information is lost between polling intervals and reducing the time the BMC needs to spend on communication
Solution Approach 2:
The CPLD acts as an intermediary between the signal sources and the BMC. It receives signals from various components, detects changes through edge detection, stores the information in its registers, and then transfers it to the BMC on demand. This intermediary role prevents information loss by capturing changes locally before they need to be communicated to the BMC, reducing both information loss and communication time
4Speed
If the CPLD stores signal changes in FIFO memory and transmits through I2C bus, then real-time data transmission is achieved, but the device complexity increases
Solution Approach 1:
The CPLD uses FIFO memory to preliminarily store signal change data before transmission to the BMC. When changes occur, the data is immediately captured and held in the FIFO buffer, ready for rapid transmission when the BMC is available. This preliminary storage action enables real-time data capture without requiring complex continuous transmission mechanisms
Solution Approach 2:
The system uses periodic I2C bus transactions combined with interrupt-driven transmission. The FIFO memory buffers data until the BMC is ready to receive it, then transmits data in periodic or interrupt-triggered batches rather than requiring complex continuous real-time transmission, achieving real-time performance with simpler periodic action
Data Source
AI summary
The present disclosure provides a complex programmable logic device (CPLD) and a communication method. The CPLD includes a data transmission module, a first in first out (FIFO) memory, and an I2C slave. The data transmission module obtains a first signal of the server, the FIFO memory obtains the first signal transmitted by the data transmission module, and the I2C slave obtains the first signal transmitted by the FIFO memory, so that the baseboard management controller (BMC) reads the first signal from the I2C slave through an I2C bus.