CPLD I2C Data Communication System for Signal Integrity
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Solution Overview
Problem
Inter-Integrated Circuit (I2C) communications in server applications face data handling issues due to strict timing requirements, leading to potential data mishandling when devices do not meet these requirements.
Innovation Solution
A data communication system comprising a complex programmable logic device (CPLD) with a signal obtaining unit, counting unit, and comparing unit that processes the SDA and SCL signals to accurately count and decode data within a clock cycle, using preset values to determine valid data transmission, thereby ensuring data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If I2C bus data transmission uses strict timing requirements, then data transmission reliability is improved, but device compatibility and ease of operation deteriorate when devices cannot meet these requirements
Solution Approach 1:
The CPLD counts the number of valid data bits in advance within each clock cycle before decoding. By performing this counting action preliminarily, the system ensures that data is properly validated against timing requirements before further processing, thus maintaining reliability while accommodating devices with varying timing capabilities
Solution Approach 2:
The CPLD acts as an intermediary device between the I2C bus and the decoding logic. It receives the SDA and SCL signals, performs intermediate counting and validation operations, and only passes properly validated data to the decoding unit. This intermediary function protects the system from timing violations while maintaining compatibility with various devices
2Reliability
If I2C bus data transmission uses strict timing requirements, then data transmission reliability is improved, but data mishandling occurs when devices do not meet these requirements
Solution Approach 1:
The system uses the SCL clock signal as a feedback reference to control the counting operation. By synchronizing the counting of valid data bits with the clock cycles, the system creates a feedback mechanism that ensures data is only processed when timing requirements are met, preventing data mishandling while maintaining reliability
Solution Approach 2:
The validity of data bits is determined in advance by counting them within the clock cycle before decoding occurs. This preliminary validation ensures that only properly timed data proceeds to decoding, preventing information loss while maintaining transmission reliability
Data Source
AI summary
A data communication system applied in an Inter-Integrated Circuit (I2C) bus includes a complex programmable logic device (CPLD) and a communication device. The CPLD includes a signal obtaining unit, a counting unit, and a comparing unit. The signal obtaining unit obtains SDA and SCL signals of the I2C bus of the communication device, and transmits same to the counting unit. The counting unit counts the valid data of the SDA within one clock cycle of the SCL signal to get a count value, and transmits the count value to the comparing unit. The comparing unit compares the count value with a second preset value, and outputs the corresponding data in decoded form according to the result of comparison.