CPLD Power Control Circuit for Static Current Reduction
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Solution Overview
Problem
Conventional complex programmable logic devices (CPLDs) face high power consumption due to sense amp technology and other circuits drawing current even in static states, leading to increased energy usage and costs, especially when interfacing chips with different voltage configurations.
Innovation Solution
A method and circuit that utilize power control signals to reduce power consumption by selectively disabling or reducing the operating voltage of circuit blocks, employing a power control circuit to manage operating voltages and enable power-down modes in specific blocks, thereby minimizing current draw across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CPLD architecture with sense amp technology is used, then logic capacity and functionality are achieved, but power consumption increases due to current draw in static state
Solution Approach 1:
The CPLD is divided into multiple independently controllable function blocks, each with its own power control signal. This segmentation allows selective powering down of unused blocks, reducing overall power consumption while maintaining necessary logic capacity in active blocks.
Solution Approach 2:
The patent introduces dynamic power control through enable signals that can selectively activate or deactivate function blocks based on operational needs. This dynamic control allows the device to adapt power consumption to actual usage patterns, addressing the static power waste problem.
2Adaptability or versatility
If multiple internal voltages are provided for interfacing chips with different voltage configurations, then adaptability increases, but power consumption and circuit complexity increase
Solution Approach 1:
Different function blocks can be supplied with different voltages based on their specific requirements. The power control circuitry enables selective voltage application to individual blocks, allowing 2.5V processors to interface with 3.3V memories without requiring all circuits to operate at maximum voltage, thus reducing overall power consumption.
Solution Approach 2:
The patent implements variable voltage control where the voltage level supplied to each function block can be independently adjusted according to its operational requirements. This parameter change capability allows the system to optimize power consumption by matching voltage levels to actual needs rather than using a fixed high voltage throughout.
3Speed
If all function blocks remain powered to maintain readiness, then operational responsiveness is maintained, but power consumption increases
Solution Approach 1:
The power control mechanism enables periodic or on-demand activation of function blocks rather than continuous operation. Blocks can be powered down when not needed and quickly activated when required, reducing average power consumption while maintaining operational responsiveness through controlled periodic operation.
Solution Approach 2:
Unnecessary power consumption is extracted or removed from the system by selectively disabling power supply to function blocks that are not currently needed. This extraction of excess power usage allows the device to operate more efficiently while maintaining readiness of only the necessary blocks.
Data Source
AI summary
A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.