CPLD-Based Server Hard Disk Clock Signal Control
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Solution Overview
Problem
Current server power management systems lack the ability for users to efficiently control and reduce power consumption of hard disks through BIOS settings, limiting user flexibility and increasing energy costs.
Innovation Solution
A server power saving system comprising a motherboard with a CPLD, clock chip, and basic I/O control chip, and a backplane with hard disk microcontrollers, allowing users to control the clock signal sent to hard disk connection ports via BIOS settings, enabling dynamic power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal is continuously sent to the hard disk connection port, then the hard disk can operate normally and access data, but the power consumption increases
Solution Approach 1:
The system implements periodic action by controlling the clock chip to send clock signals only when needed (when hard disk is detected or data access is required) rather than continuously. The CPLD receives detection signals from the hard disk microcontroller and conditionally activates the clock signal transmission, creating an on-demand periodic operation mode that reduces power consumption while maintaining operational reliability.
2Use of energy by moving object
If the clock signal is stopped to save power, then the power consumption is reduced, but the user cannot control or monitor the power saving status
Solution Approach 1:
The system implements feedback by providing a visual indicator (light signal) that reflects the power saving status. When the clock signal is stopped to save power, the indicator light shows the current state, allowing users to monitor and understand the power saving operation. This feedback mechanism enables users to control and verify the power management behavior without requiring complex interfaces.
3Device complexity
If traditional power management systems are used, then the hardware structure is simple, but the user flexibility and power control capability are limited
Solution Approach 1:
The system introduces a CPLD (Complex Programmable Logic Device) as an intermediary component between the existing hardware and the power management functionality. The CPLD receives detection signals from the hard disk microcontroller, processes the logic for clock signal control, and interfaces with the clock chip. This intermediary approach adds minimal hardware complexity while providing flexible, programmable power management capabilities and user control through BIOS settings.
Data Source
AI summary
A server power saving system includes a motherboard and a backplane. The motherboard includes a CPLD, a basic I/O control chip electrically connected with the CPLD, and a clock chip electrically connected with the CPLD. The basic I/O control chip includes a basic I/O control program The backplane includes a HD microcontroller electrically connected with the CPLD and a HD connection port electrically connected with the HD microcontroller and the clock chip. The HD microcontroller sends clock enable signal to the CPLD when a HD is electrically connected with the HD connection port. The CPLD transmits clock enable signal to the basic I/O control chip. The basic I/O control chip sends confirmation signal to the CPLD according to clock enable signal, and the CPLD determines whether to drive the clock chip to send clock signal to the HD connection port according to a content of confirmation signal.