CPLD-Controlled Sleep Power Gating for Motherboard Components
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Solution Overview
Problem
Existing power management systems in computer apparatuses fail to maximize power savings during deep sleep modes as they only turn off the main power supply or partial standby power supplies, leaving room for improvement.
Innovation Solution
A power management system that includes a first power supply for the CPLD, a second power supply for the motherboard chipset and target components, and a CPLD to control the second power supply for complete shutdown during sleep mode, ensuring all unnecessary power consumption is halted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional power management schemes turn off only the main power supply or partial standby power supplies, then the system can maintain basic functionality with minimal power off, but power savings are not maximized
Solution Approach 1:
The power supply system is segmented into multiple independent power supplies (first power supply for CPLD, second power supply for motherboard chipset and target components). This segmentation allows selective shutdown of the second power supply during sleep mode while keeping the first power supply active, maximizing power savings without completely disabling the system.
Solution Approach 2:
The CPLD acts as an intermediary control device that manages the power state of different components. It receives sleep requests from the motherboard chipset and controls the second power supply accordingly, enabling intelligent power management that balances power savings with system functionality.
2Loss of energy
If more power supplies are turned off during sleep mode to maximize power savings, then energy loss is reduced, but system reliability and wake-up capability may be compromised
Solution Approach 1:
By dividing the power supply into separate units (first power supply for CPLD, second power supply for other components), the system can selectively power down only the second power supply during sleep mode. This ensures that the CPLD remains powered and can reliably manage wake-up events, maintaining system reliability while maximizing power savings.
Solution Approach 2:
Different parts of the system have different power requirements. The CPLD requires continuous power to maintain system control capability, while other components can be fully powered down. This local quality differentiation allows the system to optimize power consumption in non-critical areas while maintaining reliability in critical areas.
Data Source
AI summary
A power management system includes a power supply unit a first power supply, a second power supply, a Complex Programmable Logic Device (CPLD), and a motherboard chipset. The first power supply receives electrical energy of the power supply unit and powers the CPLD. The second power supply receives the electrical energy of the power supply unit and powers the CPLD, the motherboard chipset, and a target component. The motherboard chipset enters a sleep mode in response to a sleep request and output a sleep instruction to the CPLD. The CPLD outputs a sleep control signal to the second power supply in response to the sleep instruction. The second power supply stops powering the motherboard chipset and the target component in response to the sleep control signal, for maximizing power saving while the power management system is in the sleep. A computer apparatus is also provided.