CPODE Isolation Structure With Layered Dielectrics for Leakage Control
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in achieving reduced contacted poly pitch (CPP) while maintaining electrical isolation and device reliability, as continuous poly on diffusion edge (CPODE) processes induce undesirable leakage currents.
Innovation Solution
Implementing a CPODE structure with multiple dielectric layers of varying material composition stacked vertically to reduce leakage current, including a fixed-charge free material for the bottom portion and an SiN-like material for the top portion, buried below the shallow trench isolation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a continuous poly on diffusion edge (CPODE) process is used to scale the contacted poly pitch (CPP), then the CPP is reduced and device density is improved, but leakage current increases and electrical isolation deteriorates
Solution Approach 1:
The CPODE structure is segmented into multiple dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) with different material compositions. Each layer serves a specific function: the bottom layer provides mechanical support, the middle layer reduces leakage current, and the top layer provides electrical isolation. This segmentation allows the structure to simultaneously achieve reduced pitch and maintained isolation.
Solution Approach 2:
Different portions of the CPODE structure are assigned different material qualities to address local requirements. The bottom portion uses a first dielectric material optimized for mechanical properties, the middle portion uses a second dielectric material specifically selected for leakage current reduction, and the top portion uses a third dielectric material for electrical isolation. This local differentiation resolves the contradiction between pitch reduction and isolation maintenance.
2Ease of manufacture
If existing CPODE processes are used to achieve reduced pitch, then manufacturing complexity is lowered, but device performance and reliability are compromised due to leakage current
Solution Approach 1:
The CPODE structure employs a composite dielectric system with three distinct dielectric layers having different material compositions. This composite approach maintains manufacturing simplicity by using standard dielectric deposition processes while achieving superior device performance through the synergistic combination of materials with complementary properties for leakage reduction and electrical isolation.
3Productivity
If scaling continues to reduce CPP, then production efficiency improves and costs decrease, but process complexity increases
Solution Approach 1:
The multi-layer dielectric CPODE structure serves multiple functions simultaneously: it provides mechanical support, reduces leakage current, maintains electrical isolation, and enables continued pitch scaling. This multi-functionality allows the structure to support further scaling to reduced CPP values without proportionally increasing process complexity, as the same layered architecture addresses multiple challenges that would otherwise require separate solutions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances device performance and reliability by reducing leakage currents and maintaining electrical isolation between adjacent active regions, while being compatible with existing processes and costing minimally.
Implementation Method 1
The first refill layer 602B-1 may include an SiO-like material, for example. In some cases, the first refill layer 602B-1 may include a fixed-charge free material, which may reduce leakage current between the substrate 202 and the first refill layer 602B-1.
Implementation Method 2
The CPODE structure 713 may provide an isolation region between the first active region 203 and the second active region 205
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a partially-fabricated semiconductor device including a dummy gate structure disposed over a semiconductor layer stack. In some embodiments, the method further includes removing the dummy gate structure and at least a portion of each semiconductor layer of the semiconductor layer stack to form a trench. In some examples, the method further includes forming one or more refill layers in a bottom portion of the trench and forming one or more refill layers in a top portion of the trench over the bottom portion of the trench. In some embodiments, the one or more refill layers in the top and bottom portions of the trench respectively define top and bottom portions of an isolation structure. In some examples, at least one refill layer of respective ones of the top and bottom portions of the isolation structure have a different material composition.