CPODE Recess Etching With Vertical Profile Protection
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Solution Overview
Problem
Damage to source/drain regions occurs during the etching process for forming a continuous polysilicon on oxide definition edge (CPODE) structure in fin-based transistors, leading to reduced semiconductor device yield and performance.
Innovation Solution
A two-step etch technique is employed, combining isotropic and anisotropic etching to form the CPODE recess, minimizing damage by reducing lateral etching and preserving the integrity of the ILD layer and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-step etching process is used to form the CPODE recess, then the etching speed is fast and productivity is high, but lateral etching damage occurs to the source/drain regions and ILD layer
Solution Approach 1:
The etching process is divided into two distinct steps: a first etching step that forms an initial recess, and a second etching step that completes the CPODE recess formation. This segmentation allows each step to be optimized independently - the first step can use more aggressive parameters for speed, while the second step uses controlled parameters to minimize lateral damage to source/drain regions and the ILD layer.
Solution Approach 2:
The first etching step performs a preliminary action by creating an initial recess structure that defines the basic geometry of the CPODE feature. This preliminary recess provides a foundation that guides subsequent etching, allowing the second step to focus on precise lateral boundary control rather than starting from a flat surface, thus reducing lateral etching damage.
2Productivity
If aggressive etching parameters are used to increase etching rate, then productivity improves, but damage to source/drain regions increases
Solution Approach 1:
The etching process parameters are segmented into two sets: aggressive parameters for the first etching step to maximize etching rate and productivity, and controlled parameters for the second etching step to protect source/drain region integrity. This segmentation resolves the contradiction by allowing high productivity when needed while preventing damage through parameter control.
Solution Approach 2:
The first etching step uses partial action by removing only a portion of the required total etch depth, using aggressive parameters that would be excessive if applied to the complete etching process. This partial aggressive etching achieves high productivity for the majority of material removal, while the remaining portion is completed with controlled parameters to prevent damage.
3Manufacturing precision
If lateral etching is increased to widen the CPODE recess, then the definition edge quality improves, but damage to adjacent ILD layer and source/drain regions worsens
Solution Approach 1:
The lateral etching function is segmented between two etching steps: the first step establishes the primary lateral dimensions with controlled precision, and the second step provides fine-tuned lateral etching to achieve the final definition edge quality. This segmentation allows each step to optimize for its specific lateral etching requirements without compromising adjacent structures.
Solution Approach 2:
Different local quality requirements for lateral etching are addressed by applying different etching conditions in different steps. The first etching step applies uniform lateral etching to establish basic dimensions, while the second step applies localized lateral etching only where definition edge quality is needed, with parameters tuned to stop before damaging adjacent ILD layer or source/drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances semiconductor device yield and performance by preventing etching damage, allowing for efficient formation of the CPODE structure while maintaining structural integrity.
Implementation Method 1
A two-step etch technique is employed, combining isotropic and anisotropic etching to form the CPODE recess
Implementation Method 2
A two-step etch technique is employed, combining isotropic and anisotropic etching to form the CPODE recess
Implementation Method 3
A two-step etch technique is employed, combining isotropic and anisotropic etching to form the CPODE recess
Data Source
AI summary
A two-step etch technique is used in a continuous polysilicon on oxide definition edge (CPODE) recess process to form a recess in which the CPODE structure is to be formed. The two-step process includes performing a first etch operation using an isotropic etch technique, in which a recess in a dummy gate structure is formed to a first depth. A second etch operation is performed using anisotropic etch technique to form the recess to a second depth. The use of the anisotropic etch technique results in a highly directional (e.g., vertical) etch of the dummy gate structure in the second etch operation. The highly directional etch provided by the anisotropic etch technique at or near the bottom of the dummy gate structure reduces, minimizes, and/or prevents etching into adjacent portions of an interlayer dielectric (ILD) layer and/or into source/drain region(s) under the portions of the ILD layer.