CPODE Recess Etching to Protect Source/Drain Regions
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Solution Overview
Problem
Damage to source/drain regions occurs during the etching process for forming a continuous polysilicon on oxide definition edge (CPODE) structure in fin-based transistors, leading to reduced semiconductor device yield and performance.
Innovation Solution
A two-step etch technique is employed, combining isotropic and anisotropic etching to form the CPODE recess, minimizing damage by reducing lateral etching and protecting the ILD layer and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching technique is used to form the CPODE recess, then the etching process is simple and fast, but damage occurs to source/drain regions and the ILD layer
Solution Approach 1:
The etching process is divided into two distinct steps: a first etching step using a first etching technique, and a second etching step using a second etching technique. This segmentation allows each step to be optimized for different purposes - the first step removes material efficiently while the second step provides precise control to prevent damage to sensitive regions, thereby resolving the contradiction between etching speed and damage prevention.
Solution Approach 2:
The patent changes the parameters of the etching process by using two different etching techniques with distinct characteristics. The first etching technique is selected for higher removal rate, while the second etching technique is selected for better selectivity and control. By changing the etching parameters (technique type, chemistry, power, pressure) between steps, the process achieves both high productivity and minimal damage.
2Loss of time
If aggressive etching is used to form the CPODE recess quickly, then manufacturing efficiency is improved, but lateral etching damages the ILD layer and source/drain regions
Solution Approach 1:
The etching process is segmented into two steps with different objectives. The first step uses aggressive etching to remove material quickly, accepting some lateral etching. The second step uses controlled etching to precisely define the final recess boundaries and remove any excess lateral etching, thereby recovering precision after sacrificing some time in the first step.
Solution Approach 2:
The patent converts the harmful lateral etching effect into a beneficial process feature. The first etching step intentionally allows lateral etching to occur, which actually helps to pre-condition the surface and remove protective layers. The second step then cleans up the boundaries, transforming what would be pure damage into a useful pre-processing action that accelerates the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances semiconductor device yield and performance by preventing etching damage, allowing for efficient formation of the CPODE structure.
Implementation Method 1
A two-step etch technique is employed, combining isotropic and anisotropic etching to form the CPODE recess
Data Source
AI summary
A two-step etch technique is used in a continuous polysilicon on oxide definition edge (CPODE) recess process to form a recess in which the CPODE structure is to be formed. The two-step process includes performing a first etch operation using an isotropic etch technique, in which a recess in a dummy gate structure is formed to a first depth. A second etch operation is performed using anisotropic etch technique to form the recess to a second depth. The use of the anisotropic etch technique results in a highly directional (e.g., vertical) etch of the dummy gate structure in the second etch operation. The highly directional etch provided by the anisotropic etch technique at or near the bottom of the dummy gate structure reduces, minimizes, and/or prevents etching into adjacent portions of an interlayer dielectric (ILD) layer and/or into source/drain region(s) under the portions of the ILD layer.