CPPGA Buffer Structure for Power Device Thermal Stress Management
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Solution Overview
Problem
Current power device packaging technologies face challenges in minimizing thermal resistance, mechanical stress, and reliability due to differences in thermal expansion coefficients between materials, leading to inefficient heat transfer and potential mechanical failures.
Innovation Solution
The introduction of a closely packed pin grid array (CPPGA) buffer structure with discrete pillars, which provides a stress-relieving mechanism that enhances thermal and electrical conductivity while accommodating different thermal expansion coefficients, allowing for a thinner thermal interface material and improved mechanical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick thermal interface material layer is used to compensate for poor contact pressure, then mechanical stress is reduced, but thermal resistance increases
Solution Approach 1:
The patent changes the physical and mechanical parameters of the thermal interface material by incorporating viscoelastic polymers with specific glass transition temperatures. This allows the material to exhibit temperature-dependent mechanical properties, being softer at operating temperatures to conform to surfaces and harder at room temperature for handling. This parameter change enables the material to provide good contact pressure without requiring excessive thickness, thus reducing thermal resistance while maintaining reliability
Solution Approach 2:
The patent employs composite thermal interface materials combining multiple components: viscoelastic polymers, thermally conductive fillers (such as aluminum oxide, silicon oxide, or zinc oxide), and optional reinforcing fibers. This composite structure provides both the mechanical compliance needed for good contact pressure distribution and the thermal conductivity needed to minimize thermal resistance, resolving the contradiction between these two requirements
2Adaptability or versatility
If materials with different thermal expansion coefficients are joined, then functional requirements are met, but mechanical stress and reliability deteriorate
Solution Approach 1:
The patent explicitly addresses thermal expansion mismatch by selecting thermal interface materials with thermal expansion coefficients intermediate between the semiconductor device and the substrate. The viscoelastic polymer matrix and filler combination allows the material to expand and contract with temperature changes without generating excessive stress, accommodating the different thermal expansion coefficients of adjacent materials while maintaining joint integrity and reliability
Solution Approach 2:
The patent changes the thermal and mechanical parameters of the interface material to match those of the surrounding components. By adjusting the filler content, polymer matrix composition, and crosslinking density, the material's thermal expansion coefficient, modulus of elasticity, and other parameters are optimized to bridge the gap between materials with different thermal expansion coefficients, reducing stress and improving reliability
3Ease of manufacture
If peripheral bolts are used for assembly, then manufacturing is simplified, but contact pressure uniformity deteriorates
Solution Approach 1:
The patent changes the mechanical parameters of the thermal interface material to compensate for the non-uniform pressure distribution caused by peripheral bolting. The viscoelastic material's ability to flow and conform under compression, combined with its temperature-dependent modulus, allows it to redistribute pressure evenly across the contact surface despite the localized loading from peripheral bolts, thus maintaining manufacturing simplicity while achieving pressure uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces thermal resistance, increases reliability, and allows for a more efficient heat transfer path, enabling higher power density and improved long-term performance by managing thermal and mechanical stresses effectively.
Implementation Method 1
buffer structure with a plurality of discrete pillars closely packed together... provides a stress-relieving mechanism that enhances thermal and electrical conductivity while accommodating different thermal expansion coefficients
Implementation Method 2
significantly reduces thermal resistance, increases reliability, and allows for a more efficient heat transfer path
Implementation Method 3
provides a stress-relieving mechanism that enhances thermal and electrical conductivity
Data Source
AI summary
A packaging method for power devices with optimized stacks of layers comprising different thermal expansion coefficients, the method including a stress relieving buffer technology designed to improve the thermal, electrical and mechanical contact between chips and electrodes. We disclose herein a buffer structure to provide stress relief between two layers of an electronic device, the buffer structure comprising: a plurality of discrete pillars closely packed together such that there is substantially no air gap between the plurality of conductive pillars, and wherein a height of each pillar is greater than a thickness of said pillar.