Hierarchical Timing Analysis Using CPPR Database
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Solution Overview
Problem
The complexity of designing integrated circuits, particularly with giga gate scale designs, leads to challenges in achieving timing closure due to overly pessimistic timing budgets and the difficulty in accurately analyzing clock signal timing across hierarchical blocks, resulting in increased design time and resource usage.
Innovation Solution
A computer-implemented method using a common path pessimism removal (CPPR) database to generate block-level context constraints, perform delay calculations, and physical optimizations, allowing for hierarchical timing analysis and improved timing accuracy by propagating CPPR tags through the timing graph, thereby adjusting timing at block-level input ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If automatic timing budgeting is performed using worst case scenarios, then timing budgets are generated automatically, but the timing budgets become overly pessimistic leading to errors
Solution Approach 1:
The patent applies local quality by transitioning from global worst-case timing budgets to block-level specific timing budgets. Each block receives customized timing constraints based on its actual clock paths and signal routing, rather than using a uniform pessimistic budget for the entire chip. This localized approach maintains automation while improving precision by accounting for actual block characteristics.
Solution Approach 2:
The patent introduces block-level timing constraints as an intermediary between chip-level automatic timing generation and block-level design verification. These intermediate constraints serve as a bridge that translates automated chip-wide timing budgets into accurate block-specific constraints, eliminating the need for manual correction while preventing overly pessimistic timing allocations.
2Device complexity
If hierarchical design is implemented for giga gate chip designs, then design complexity is reduced, but the evaluation of overall circuit design becomes complicated
Solution Approach 1:
The patent applies segmentation by dividing the chip into hierarchical blocks with independent timing analysis capabilities. Each block can be evaluated separately using block-level timing constraints, and the results are aggregated to provide overall chip timing validation. This segmentation maintains design simplicity at the block level while enabling comprehensive evaluation at the chip level through systematic constraint propagation.
Solution Approach 2:
The patent implements feedback mechanisms where block-level timing analysis results feed back into chip-level timing validation. The block-level context constraints are generated based on chip-level timing requirements and propagated down to blocks, with results feedback to verify overall timing closure. This feedback loop simplifies evaluation by providing clear pass/fail criteria at each hierarchy level.
3Reliability
If multiple paths are analyzed that share common input and output, then comprehensive timing analysis is performed, but timing analysis complexity increases
Solution Approach 1:
The patent merges common clock paths and common input/output ports across multiple signal paths into unified block-level timing constraints. Instead of analyzing each path independently which would be computationally intensive, the patent combines shared elements and applies timing constraints at the block level, reducing analysis complexity while maintaining comprehensive coverage of all paths that share common infrastructure.
Data Source
AI summary
The present disclosure relates to a system for use in electronic circuit design. The system may include a computing device configured to receive, using at least one processor, an electronic design. The at least one processor may be further configured to generate a common path pessimism removal (“cppr”) database configured to store one or more cppr tags obtained from an initial timing analysis of at least a portion of the electronic design. The at least one processor may be further configured to apply the one or more cppr tags during a block-level timing analysis.