Design Assistance Device for CPU-Accelerator Allocation
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Solution Overview
Problem
Existing design assistance devices for computer systems with CPUs and accelerators face challenges in optimizing process and data arrangement under communication band and memory capacity constraints, leading to increased design workloads and suboptimal system performance.
Innovation Solution
A design assistance device that includes program analysis, computing unit implementation scheme evaluation, and design space search capabilities to extract and analyze processes and data access relationships, evaluate resource usage, delay, and communication band, and generate optimal allocation candidates for CPU and accelerator combinations based on hardware specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing design assistance devices are used for CPU and accelerator systems, then basic design support is provided, but design workloads increase and system performance becomes suboptimal due to inability to optimize under communication band and memory capacity constraints
Solution Approach 1:
The patent segments the design assistance functionality into three distinct modules: program analysis means for extracting and analyzing process-data relationships, computing unit implementation scheme evaluation means for evaluating resource usage and communication band, and design space search means for generating optimal allocation candidates. This segmentation allows each module to specialize in specific tasks, improving overall design efficiency and reducing workload while maintaining optimization capability under communication band and memory constraints
Solution Approach 2:
The patent introduces an intermediary design assistance device that acts as a mediator between the programmer and the complex CPU-accelerator system. This intermediary automatically performs program analysis, evaluates implementation schemes, and searches design spaces, thereby reducing the designer's workload while ensuring optimal system performance under various constraints including communication band and memory capacity
2Reliability
If process and data arrangement are not optimized under communication band constraints, then design workloads increase, but communication band constraint violations occur leading to reduced system performance
Solution Approach 1:
The patent applies preliminary action by performing program analysis and design space search before final system implementation. The design assistance device evaluates multiple allocation candidates and selects optimal arrangements that satisfy communication band constraints before deployment, preventing constraint violations and reducing the need for iterative redesign, thereby improving reliability while managing design workload
Solution Approach 2:
The patent implements feedback mechanisms where the computing unit implementation scheme evaluation means evaluates resource usage and communication band for each candidate, and the design space search means uses this feedback to refine allocation candidates. This iterative feedback process ensures that final designs satisfy communication band constraints while optimizing system performance, balancing reliability improvement with controlled design workload
Data Source
AI summary
A design assistance method executed by a design assistance device for a computer system including a CPU and an accelerator, the design assistance method includes: extracting, from an input program described in a high-level language, a process including a function and data including a variable, and analyzing a relationship between a process and data, the relationship including an amount of access from the process to the data, based on a number of times of execution of the function or a loop; evaluating, for the acquired process, a used amount of resource, a delay, and a communication band of the accelerator, based on a hardware specification; and generating, for the acquired process and data, candidates represented by a combination of allocations to the CPU and the accelerator, and acquiring and presenting, for each of the candidates, a used amount of resource, a communication band, and performance of the input program.