CPU Arithmetic Unit Power Analysis Attack Resistance
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Solution Overview
Problem
Existing methods for improving resistance to power analysis attacks in central processing units (CPUs) either require significant redesign, lower clock frequencies, or increase program complexity, making them inefficient for practical implementation.
Innovation Solution
A CPU design that incorporates an arithmetic unit capable of performing operations using irrelevant data in the first clock cycle, with a control unit managing the arithmetic processing to change internal and output signals to states irrelevant to arithmetic operations, thereby enhancing resistance to power analysis attacks without altering programs or reducing clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated change instruction is inserted to change internal signals to states irrelevant to arithmetic operations, then resistance to power analysis attack is improved, but program size increases and programming complexity increases
Solution Approach 1:
The CPU automatically changes internal signals to states irrelevant to arithmetic operations without requiring programmer intervention. The control unit detects the execution cycle and autonomously inserts the inactive phase, making the system self-protecting against power analysis attacks while eliminating the need for complex programming
2Reliability
If internal signals are changed at the rising edge of clock signal and returned at the falling edge, then resistance to power analysis attack is improved, but clock frequency must be lowered
Solution Approach 1:
The CPU performs the signal change operation in advance at the beginning of the execution cycle (first clock cycle) before the actual arithmetic operation. This preliminary action completes the protection mechanism within the normal clock cycle timing, allowing the system to maintain high clock frequencies while still providing effective protection against power analysis attacks
3Reliability
If a dedicated change instruction is inserted before arithmetic operations, then resistance to power analysis attack is improved, but execution time increases
Solution Approach 1:
The patent merges the signal change operation with the arithmetic operation execution cycle. The inactive phase is integrated into the first clock cycle of the arithmetic operation, combining the protection mechanism with the normal execution flow. This eliminates the need for separate instruction cycles, so the total execution time does not increase beyond the normal arithmetic operation time
Data Source
AI summary
There is a need to provide a central processing unit capable of improving the resistance to power analysis attack without changing programs, lowering clock frequencies, and greatly redesigning a central processing unit of the related art. In a central processing unit, an arithmetic unit is capable of performing arithmetic operation using data irrelevant to data stored in a register group. A control unit allows the arithmetic unit to perform arithmetic processing corresponding to an incorporated instruction. At this time, the control unit allows the arithmetic unit to perform arithmetic processing using the irrelevant data during a first one-clock cycle.