CPU-Bus JTAG Access for Modular PLD Reprogramming

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Solution Overview

Problem

Existing programmable logic devices (PLDs) face challenges in scalability and flexibility due to their serial architecture, which makes it difficult to add or remove devices from a system without disrupting the entire chain, and requires complex wiring, especially in distributed systems with multiple PLDs.

Innovation Solution

Implementing a processor programmable PLD system that uses a CPU interface to access and program individual PLDs independently through a JTAG interface, reducing the need for dedicated wiring and allowing for modular, scalable architectures by using a bus to connect multiple PLDs with minimal additional wires.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a serial JTAG chain architecture is used to program multiple PLDs, then the wiring complexity is reduced, but the system becomes sensitive to device removal or failure and lacks flexibility for adding or removing PLDs

Engineering Contradiction:

Improvewiring complexityVSAvoidflexibility for adding or removing PLDs

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent divides the programming system into independent parallel segments, where each PLD can be individually accessed through the CPU bus rather than being part of a single serial chain. This segmentation allows any PLD to be programmed independently without affecting others, resolving the contradiction between reduced wiring complexity and lost flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The CPU bus is given multiple functions: it serves both as the primary system bus for normal operation and as a programming interface for configuring PLDs. This multi-functionality eliminates the need for separate dedicated programming wires, achieving both wiring simplification and flexible individual access to each PLD.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If dedicated I/O pins and wires are allocated for programming PLDs, then reliable programming is achieved, but the wiring complexity increases especially in distributed systems with multiple PLDs

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidwiring complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the CPU bus multi-functional by using it both for normal system operation and for PLD programming. This eliminates the need for separate dedicated programming wires while maintaining reliable programming capability, thus resolving the contradiction between programming reliability and wiring complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the programming function with the existing CPU bus infrastructure, combining two previously separate functions (system operation and programming) into a single shared resource. This consolidation reduces the total wire count while preserving programming reliability through the robust CPU bus interface.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If a CPU bus interface is used to program individual PLDs independently, then flexibility and scalability are improved, but additional interface logic is required in each PLD

Engineering Contradiction:

Improveflexibility for adding or removing PLDsVSAvoidinterface logic in PLD

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary I/O register in each PLD that acts as a bridge between the CPU bus and the PLD's internal configuration memory. This intermediary simplifies the interface logic required in each PLD while enabling flexible independent access through the CPU bus, resolving the contradiction between scalability and interface complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Device complexity

If serial programming architecture is used, then wiring is simplified, but programming speed is limited by the serial communication rate

Engineering Contradiction:

Improvewiring complexityVSAvoidprogramming speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent repurposes the high-speed CPU bus for programming operations, eliminating the speed limitation of serial JTAG interfaces. The CPU bus can transfer data in parallel at much higher rates, simultaneously achieving fast programming speeds while maintaining wiring simplicity through the shared bus interface.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8174287B2Processor programmable PLD device

Publication Date: 2012.05.08 AVAYA INC

AI summary

A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.