CPU Cache Efficiency via Concurrent Data Processing

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Solution Overview

Problem

Current data processing systems face inefficiencies in managing concurrent data processing operations, particularly in ensuring that multiple processing tasks, such as deduplication, compression, and encryption, are synchronized to avoid re-fetching data chunks from memory and improve processing efficiency.

Innovation Solution

Implementing a method where first and second data processing operations on a data chunk are performed in parallel and synchronized to ensure completion before proceeding with another chunk, with options for parallel or sequential execution within a single thread, utilizing techniques like digest computation and compression/decompression inline with I/O path processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple data processing operations are performed sequentially on data chunks, then processing simplicity is maintained, but processing efficiency and I/O response times deteriorate due to redundant data fetching from memory

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments data into fixed-size chunks and processes them through multiple parallel operations (deduplication, compression, encryption) simultaneously. Each processing operation works on the same data chunk in parallel, eliminating the need to re-fetch data from memory for each operation, thereby improving processing efficiency while maintaining manageable complexity through structured chunk-based processing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges multiple data processing operations (deduplication, compression, encryption) into a single parallel processing pipeline that operates on data chunks simultaneously. By combining these operations into an integrated inline processing system, the patent achieves improved efficiency without proportionally increasing complexity, as all operations share the same data fetch and processing framework

Inventive Principle:
Principle #5Merging (Combining)

2Loss of time

If data chunks are re-fetched from memory for each processing operation, then processing simplicity is maintained, but I/O response times and system performance deteriorate

Engineering Contradiction:
ImproveI/O response timeVSAvoiddata management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent performs preliminary data fetching and loading of data chunks into memory before initiating multiple parallel processing operations. By preparing the data in advance and keeping it in memory during parallel processing, the system eliminates repeated I/O operations, significantly reducing I/O response time while the data management complexity is contained through structured chunk-based memory management

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuous useful action by maintaining data chunks in memory and having multiple processing operations (deduplication, compression, encryption) execute simultaneously without interruption or re-fetching. This continuous parallel processing eliminates idle time between operations and maintains high system performance, with data management complexity handled through coordinated thread synchronization

Inventive Principle:
Principle #20Continuity of useful action

3Speed

If parallel processing operations are implemented without synchronization, then processing speed is improved, but data integrity and processing correctness deteriorate due to race conditions

Engineering Contradiction:
Improveprocessing speedVSAvoidprocessing correctness
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements synchronization mechanisms that provide feedback between parallel processing threads to ensure data integrity. Thread synchronization primitives monitor and coordinate the progress of parallel operations, ensuring that processing correctness is maintained while still allowing parallel execution to achieve high processing speed. The feedback mechanism detects and resolves potential race conditions without serializing the entire processing pipeline

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11514001B2Concurrent computations operating on same data for CPU cache efficiency
Publication Date: 2022.11.29 EMC IP HLDG CO LLC
  • US11514001B2 patent drawing
  • US11514001B2 patent drawing
  • US11514001B2 patent drawing

AI summary

Techniques for CPU cache efficiency may include performing concurrent processing, such as for first and second data operations, in a synchronized manner that prevents loading the same data chunk into the CPU cache more than once. Processing may include synchronizing the first and second data operations with respect to a first data chunk to ensure that both the first and second data operation processing has completed prior to proceeding with performing such processing on a second data chunk. The first and second data operations may be any two of deduplication, encryption, and compression, performed inline as part of the data path. In one embodiment, the first and second data operations for the first data chunk may be performed in parallel or sequentially where neither data operation proceeds with another data chunk until processing of the first and second data operations is complete for the first data chunk.