CPU Cache Coherence Directory Segmentation for NUMA Scalability
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Solution Overview
Problem
In information processing systems using NUMA technology, the amount of directory information increases significantly with the number of central processing units, leading to inefficient data communication and scalability issues.
Innovation Solution
A central processing unit is configured to classify itself and other CPUs into groups, writing presence information to main memory indicating whether data is held in cache memories within each group, thereby reducing the amount of directory information and optimizing data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If presence bits are managed for each individual CPU, then cache coherence can be accurately tracked, but the amount of directory information increases significantly with the number of CPUs
Solution Approach 1:
The patent segments the presence bit management by grouping CPUs into sets, where each set is associated with a specific cache line. Instead of tracking individual CPU presence bits for all cache lines, the system divides the directory into multiple sets, each managing presence information for a subset of CPUs. This segmentation reduces the total directory information required while maintaining cache coherence tracking accuracy.
Solution Approach 2:
The patent introduces a new dimensional organization to the directory structure by arranging directory entries in a two-dimensional layout: one dimension for cache line sets and another for CPU groups. This dimensional reorganization allows the system to manage presence bits more efficiently by exploiting spatial locality and reducing the overall directory size needed to track cache coherence across multiple CPUs.
2Productivity
If the number of CPU nodes is increased to meet performance requirements, then system performance improves, but the amount of directory information increases proportionally
Solution Approach 1:
The patent applies segmentation by dividing the directory into multiple sets, where each set manages presence information for a specific group of CPUs. This allows the system to scale to a larger number of CPU nodes without proportionally increasing the total directory information, as each directory set independently manages a subset of CPUs rather than requiring a complete presence bit map for all CPUs across all cache lines.
Solution Approach 2:
The patent implements partial action by having each directory set manage presence information only for relevant CPU groups rather than maintaining complete presence information for all CPUs in the system. This partial management approach reduces the overall directory information requirement while still enabling effective cache coherence tracking for the scaled system.
3Reliability
If presence bits are expanded to cover all CPU nodes, then all cache locations can be tracked, but unnecessary data communication occurs during invalidation processes
Solution Approach 1:
The patent segments the invalidation process by directing invalidation requests only to the specific CPU groups associated with the relevant directory set, rather than broadcasting to all CPUs in the system. This targeted approach reduces unnecessary data communication while maintaining reliable cache location tracking, as each directory set independently manages invalidation for its associated CPU groups.
Solution Approach 2:
The patent introduces directory sets as intermediaries between the cache coherence management system and individual CPU groups. These directory sets act as mediators that receive invalidation requests and selectively forward them only to the relevant CPU groups, thereby reducing unnecessary communication overhead while ensuring that all relevant CPUs receive the invalidation signals they need.
Data Source
AI summary
A central processing unit, connected to a main memory among a plurality of central processing units each including a cache memory, includes a control unit. The control unit executes a process including: classifying the plurality of central processing units into a smaller number than a total number of the plurality of central processing units, and writing to the main memory presence information indicating whether or not the same data as data stored in the main memory is held in a cache memory included in any of the central processing units that belong to a corresponding central processing unit group, for each central processing unit group of a plurality of central processing unit groups obtained by the classifying.