CPU Clock Frequency Adjustment for Peak Power Reduction

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Solution Overview

Problem

Conventional power saving technologies in portable computer systems, such as clock gating and dynamic voltage and frequency scaling, are ineffective in reducing peak power consumption, leading to reduced battery life and inefficient battery power utilization.

Innovation Solution

A method for adjusting the clock frequency of a processing unit based on its busyness ratio and the operation state of peripheral units, using a frequency adjustment device and parameter setting device to dynamically adjust the CPU clock frequency within predefined ranges, thereby reducing peak power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional power saving technologies (clock gating and DVFS) are used, then average power consumption is reduced, but peak power consumption remains high

Engineering Contradiction:
Improveaverage power consumptionVSAvoidpeak power consumption
Core Design Contradiction:
Loss of energyVSPower

Solution Approach 1:

The patent applies dynamics by making the clock frequency adjustable and adaptive. The system dynamically changes the clock frequency based on real-time detection of peak power consumption conditions, transitioning from static or average-based frequency control to dynamic, condition-responsive frequency adjustment. This allows the system to respond to peak power demands and prevent battery overheating while maintaining efficient average power consumption.

Inventive Principle:
Principle #15Dynamics

2Duration of action of stationary object

If clock frequency is continuously adjusted to reduce peak power consumption, then battery life is extended, but system complexity increases

Engineering Contradiction:
Improvebattery lifeVSAvoidfrequency adjustment mechanism complexity
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The patent implements feedback by detecting actual power consumption conditions and using this information to adjust clock frequency. The system monitors power consumption in real-time and responds accordingly, creating a closed-loop control mechanism. This feedback approach allows the system to extend battery life by preventing peak power conditions without requiring overly complex predictive or reactive mechanisms, as the adjustment is directly driven by measured power consumption data.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8769322B2Method for adjusting clock frequency of a processing unit of a computer system and related device
Publication Date: 2014.07.01 MEDIATEK INC
  • US8769322B2 patent drawing
  • US8769322B2 patent drawing
  • US8769322B2 patent drawing

AI summary

A method for adjusting clock frequency of a processing unit of a computer system includes calculating a busyness ratio of the processing unit according to a status signal provided by the processing unit, determining whether the busyness ratio is in a busyness ratio range, when the busyness ratio is not in the busyness ratio range, determining whether a calculation result generated according to a clock frequency of the processing unit and a frequency difference is in a frequency range, and when the calculation result is in the frequency range, adjusting the clock frequency of the processing unit according to the calculation result and outputting the adjusted clock frequency to a clock generator, wherein the busyness ratio range, the frequency range and the frequency difference are decided according to an operation state of a peripheral unit of the computer system.