CPU Clock Generation Using Pulse Skipping for Low-Latency Scaling
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Solution Overview
Problem
Conventional clock management techniques in computer systems face latency issues when adjusting system clock frequencies, particularly in systems with multiple phase-locked loops (PLLs), which can lead to prolonged re-locking times and synchronization challenges.
Innovation Solution
The implementation of a programmable clock generator system that uses multiple clock generators to independently adjust frequencies without modifying the PLL's frequency, employing pulse skipping to achieve a wide frequency range and reduce latency, allowing for efficient frequency changes in modern microprocessor systems with multiple clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the system clock frequency is adjusted by changing a frequency of a phase locked loop (PLL), then the system can achieve optimal power savings at a given performance level, but there is a latency of several hundred microseconds before the PLL re-locks and the system can resume normal operation
Solution Approach 1:
The patent divides the clock management function into two independent components: a PLL that maintains a stable reference frequency and a programmable clock generator that adjusts output frequencies. This segmentation allows frequency changes without PLL re-locking, reducing latency while maintaining power efficiency.
Solution Approach 2:
The programmable clock generator acts as an intermediary between the stable PLL reference and the variable frequency requirements of different system components. It translates the stable reference into adjustable clock signals, enabling frequency changes without disturbing the PLL's locked state.
2Adaptability or versatility
If multiple PLLs are employed to provide clock signals for various subsystems, then each subsystem can have independent clock control, but the system latency assumes the latency of the PLL with the greatest re-locking latency and synchronization becomes complex
Solution Approach 1:
The patent employs a single PLL serving as a universal reference source for all subsystems, with individual programmable clock generators providing subsystem-specific frequency adjustments. This universal approach eliminates the need for multiple PLLs while maintaining independent clock control capability.
Solution Approach 2:
The patent merges the frequency stabilization function (performed by the PLL) with the frequency adjustment function (performed by programmable clock generators). This combination allows multiple subsystems to have independent clock control through their respective generators while sharing a common stable reference, avoiding synchronization issues.
3Adaptability or versatility
If multiple PLLs are used to provide respective clock signals for various subsystems, then each subsystem can operate at optimal frequencies, but synchronization of respective clock signals requires relatively sophisticated design solutions
Solution Approach 1:
The patent applies local quality by allowing each programmable clock generator to independently adjust its output frequency based on the specific requirements of its associated subsystem, while all generators share a common PLL reference. This enables frequency optimization at each subsystem level without requiring complex inter-subsystem synchronization mechanisms.
Data Source
AI summary
A processor (400) includes a clock source (402), a central processing unit (CPU) (408), and a clock generator (404). The clock source (402) includes an output for providing a periodic clock signal. The CPU (408) includes an input for receiving a CPU clock signal. The clock generator (404) includes a first input coupled to the output of the clock source (402), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (408). The clock generator (404) provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.