Periodic CPU Core Diagnostics in Automotive OS
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Solution Overview
Problem
Autonomous driving systems face challenges in meeting stringent functional safety requirements due to the need for periodic CPU core diagnostics, which disrupt real-time operations and require complex synchronization, especially with Hyper-Threading technology, making it difficult to achieve ASIL-B certification for CPUs in automotive applications.
Innovation Solution
Implementing periodic Structural Based Functional Tests (SBFTs) within the Operating System during run-time using the inherent real-time thread scheduling capabilities, allowing flexible scheduling and concurrent execution on cores without disabling Hyper-Threading, and utilizing a Test Manager logic to manage FTTI intervals and interrupt handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic CPU core diagnostics are implemented to meet functional safety requirements, then reliability is improved, but real-time operation performance deteriorates due to disruptions and complex synchronization needs
Solution Approach 1:
The patent segments the CPU cores into different groups and divides diagnostic testing into separate time intervals. By segmenting cores into first and second groups and alternating diagnostic execution between them, the system can perform safety diagnostics without blocking all cores simultaneously, thus maintaining real-time operation performance while ensuring functional safety coverage.
Solution Approach 2:
The patent implements periodic diagnostic testing at specific time intervals (FTTI - Fault Tolerant Time Interval) rather than continuous monitoring. This periodic action allows the system to perform safety checks at required intervals while leaving cores available for real-time work between diagnostic cycles, resolving the contradiction between reliability and productivity.
2Device complexity
If Hyper-Threading is disabled to simplify synchronization for diagnostics, then device complexity is reduced, but productivity is lost due to reduced core utilization
Solution Approach 1:
The patent dynamically manages diagnostic execution by creating and destroying test threads at appropriate times. The Test Manager logic dynamically adjusts the testing state of CPU cores, allowing Hyper-Threading to remain enabled while managing complexity through dynamic thread creation and destruction rather than static synchronization mechanisms.
Solution Approach 2:
The patent introduces a Test Manager logic as an intermediary component that coordinates diagnostic testing between different CPU cores and manages the interaction with Hyper-Threading technology. This intermediary layer handles the complexity of synchronization and timing, allowing Hyper-Threading to remain enabled without compromising diagnostic accuracy or system stability.
3Measurement precision
If diagnostics are executed on all cores simultaneously to maximize coverage, then measurement precision is improved, but device complexity increases due to synchronization requirements
Solution Approach 1:
The patent segments CPU cores into multiple groups (first group and second group) and executes diagnostics on different groups at different times. This segmentation achieves comprehensive measurement precision through multiple diagnostic cycles while avoiding the complexity of synchronizing all cores simultaneously, as each cycle only requires coordination within a specific group.
Solution Approach 2:
The patent uses periodic diagnostic cycles that systematically rotate through different core groups. By repeating diagnostic actions periodically across multiple cycles, the system achieves complete coverage of all cores without requiring complex real-time synchronization, as each periodic cycle operates independently on designated cores.
Data Source
AI summary
Methods and apparatus relating to characterizing proximity risks within a radio mesh are described. In an embodiment, test manager logic causes periodic testing of one of a first group of processor cores or a second group of processor cores. Each of the first group of processor cores or the second group of processor cores comprises one or more processor cores of a multi-core processor. Memory stores information corresponding to the period testing of the first group of processor cores and the second group of processor cores. A fault signal is to be generated in response to completion of the period testing outside a Fault Tolerant Time Interval (FTTI). Other embodiments are also disclosed and claimed.