CPU Core Grouping to Avoid Inter-CPU Bus Bottlenecks
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Solution Overview
Problem
Data passing between applications and accelerators in a complex application executed across separate physical CPUs in an information processing apparatus leads to delays due to the bottleneck of the inter-CPU bus, resulting in decreased processing speed and performance.
Innovation Solution
Execute multiple applications within a complex application on a single physical CPU using its CPU cores and deploy accelerators under the same CPU, minimizing data passing through the inter-CPU bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If applications are executed on separate physical CPUs to utilize more processing resources, then processing capacity is improved, but data transfer speed deteriorates due to inter-CPU bus bottleneck
Solution Approach 1:
The system segments applications into different groups (first group and second group) and assigns each group to execute on CPU cores within the same physical CPU. This segmentation prevents data transfer across inter-CPU buses while maintaining utilization of multiple CPU cores, thus resolving the contradiction between processing capacity and data transfer speed.
Solution Approach 2:
The patent merges multiple applications that require frequent data interaction into the same execution group, ensuring they run on the same physical CPU. This combining strategy allows these applications to share the same processing resource without incurring inter-CPU communication overhead, thereby maintaining high data transfer speed while utilizing multiple cores for improved processing capacity.
2Power
If accelerators are deployed to applications on separate physical CPUs, then processing power is improved, but communication delay increases due to inter-CPU bus bottleneck
Solution Approach 1:
The system applies local quality by deploying accelerators specifically to applications within the same execution group that run on the same physical CPU. This localized deployment ensures that data transfer between applications and their dedicated accelerators occurs within the same CPU, avoiding inter-CPU bus delays while maintaining enhanced processing power through accelerator utilization.
3Adaptability or versatility
If applications are distributed across multiple physical CPUs, then resource utilization is improved, but processing speed deteriorates due to inter-CPU data passing delays
Solution Approach 1:
The patent implements dynamic resource allocation by allowing applications to be flexibly assigned to execution groups based on their data interaction patterns. Applications requiring frequent communication are dynamically grouped together on the same physical CPU, while less interactive applications can be distributed across different CPUs. This dynamic approach optimizes both resource utilization and processing speed adaptively.
Data Source
AI summary
An information processing apparatus includes a plurality of physical CPUs and a controller. The plurality of physical CPUs each includes a plurality of CPU cores. The controller performs control of selecting two or more CPU cores that are caused to execute an application to be executed using the two or more CPU cores, from one physical CPU of the plurality of physical CPUs.