Multi-Core CPU Core Layout for Balanced Thermal and Power Load
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Solution Overview
Problem
Existing CPU architectures face issues of imbalanced core distribution leading to inefficient power and thermal management, resulting in reduced overall performance due to sequential core disabling and uneven utilization of interconnect resources.
Innovation Solution
A core distribution optimizer that uniformly distributes enabled and disabled cores across core clusters in a multi-die CPU by considering physical locations and arrangement, using a novel algorithm to balance the distribution of cores in two dimensions, ensuring optimal utilization of CPU capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sequential top-down core disabling is used, then implementation simplicity is improved, but core distribution balance deteriorates
Solution Approach 1:
The patent segments the core disabling process into multiple passes, where each pass targets specific regions of the mesh (e.g., row-major or column-major segments) rather than disabling all cores at once. This segmentation allows balanced distribution while maintaining simple implementation through iterative region-based processing.
Solution Approach 2:
The patent introduces a new dimension to core disabling by considering both row and column dimensions of the mesh simultaneously. Instead of sequential top-down disabling, the system uses two-dimensional blocking to select cores for disabling, achieving balanced distribution across the mesh while keeping the implementation straightforward through systematic region selection.
2Ease of operation
If sequential core disabling is used, then operational simplicity is improved, but interconnect resource utilization balance deteriorates
Solution Approach 1:
The patent segments the mesh into multiple regions (e.g., quadrants or blocks) and applies core disabling independently to each segment. This ensures that interconnect resources are evenly distributed across different regions, preventing congestion in any single area while maintaining simple operational procedures through systematic region-based processing.
Solution Approach 2:
The patent applies different disabling strategies to different local regions of the mesh based on their specific characteristics and interconnect utilization patterns. Each region is processed with consideration for its local interconnect demands, achieving balanced resource utilization while keeping the overall operation simple through localized optimization.
3Ease of operation
If sequential core disabling is used, then implementation simplicity is improved, but thermal balance deteriorates
Solution Approach 1:
The patent uses two-dimensional blocking to select cores for disabling, considering both row and column positions. This spatial distribution approach prevents concentration of heat-generating active cores in specific areas, achieving thermal balance across the chip while maintaining simple implementation through systematic multi-dimensional region selection.
Solution Approach 2:
The patent segments the mesh into multiple spatial regions and applies core disabling across different segments. This segmentation distributes the thermal load more evenly across the chip by preventing clustering of active cores in any single region, achieving thermal balance while keeping the implementation straightforward through iterative region-based processing.
Data Source
AI summary
Systems, methods, and other embodiments associated with distributing cores in a multi-core and/or multi-die CPU are described. In one embodiment, a core distribution system is configured to determine a physical arrangement of a plurality of cores in one or more core clusters of a CPU including rows and columns of cores. Enabled cores and disabled cores are identified within the physical arrangement. A number of target cores to be disabled from the physical arrangement are identified by selecting the target cores to create a uniform physical distribution of disabled cores and enabled cores throughout the physical arrangement of the enabled cores and the disabled cores. The system then disables the identified target cores.