CPU Core Load Balancing via IO Polling Cadence Adjustment

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Solution Overview

Problem

In scenarios where a file application is not CPU-balanced and runs only on a subset of CPU cores, it can cause performance issues such as high latency for input/output (IO) requests, degrading both average and tail IO latency, and limiting CPU utilization despite available cycles.

Innovation Solution

A method that monitors CPU core utilization and adjusts the operating system thread IO polling cadence based on the utilization and average IO latency of each CPU core, decreasing the polling cadence if the IO latency exceeds a threshold and CPU utilization is below a certain level to balance CPU operations across cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a file application runs on a subset of CPU cores, then the file application can execute with dedicated resources, but the IO latency increases and CPU utilization is limited

Engineering Contradiction:
Improvefile application executionVSAvoidIO latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic load balancing by continuously monitoring CPU core utilization and IO latency metrics, then adjusting the distribution of file application workloads across CPU cores in real-time. This dynamic adaptation allows the system to optimize both file application execution and IO response times based on current system state, resolving the contradiction between dedicated resource allocation and responsive IO handling.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by adjusting the polling cadence of OS threads based on monitored CPU utilization and IO latency thresholds. When IO latency exceeds thresholds or CPU utilization is suboptimal, the system modifies scheduling parameters to redistribute workloads, thereby improving both file application performance and IO responsiveness without requiring static resource allocation.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If a file application runs on a subset of CPU cores, then resource allocation is simplified, but CPU utilization is limited even when cycles are available

Engineering Contradiction:
Improveresource allocationVSAvoidCPU utilization
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent enables CPU cores to serve multiple functions dynamically. The same CPU cores that handle file application workloads can also service block IO requests and other system tasks. By implementing a load balancing mechanism that monitors and redistributes workloads across all available CPU cores, the system achieves high utilization while maintaining simplified resource management through centralized control rather than dedicated allocations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements self-service load balancing where the CPU resource management automatically adjusts workload distribution based on monitored performance metrics. The load balancing mechanism autonomously detects underutilized CPU cores and redistributes file application workloads to these cores without external intervention, thereby maximizing CPU utilization while maintaining ease of resource allocation through automated decision-making.

Inventive Principle:
Principle #25Self-service

3Speed

If IO polling cadence is increased, then IO responsiveness improves, but CPU utilization becomes unbalanced and latency increases on certain cores

Engineering Contradiction:
ImproveIO responsivenessVSAvoidlatency on certain cores
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies local quality optimization by adjusting IO polling cadence independently for each CPU core based on its specific workload characteristics and performance metrics. Rather than applying a uniform polling rate across all cores, the system monitors per-core IO latency and utilization, then tailors the polling cadence for OS threads on each core to its local conditions. This allows high polling rates on cores needing responsiveness while using lower rates on cores where aggressive polling would cause imbalance and increased latency.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11494236B2System and method for sharing central processing unit (CPU) resources with unbalanced applications
Publication Date: 2022.11.08 EMC IP HLDG CO LLC
  • US11494236B2 patent drawing
  • US11494236B2 patent drawing
  • US11494236B2 patent drawing

AI summary

A method, computer program product, and computing system for monitoring utilization of each central processing unit (CPU) core of a plurality of CPU cores. An average input/output (IO) latency for an operating system thread executing on the CPU core of the plurality of CPU cores may be determined. The operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core may be adjusted based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores.