CPU Core Migration for Latency and Throughput Trade-offs

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Solution Overview

Problem

Conventional multi-core processors face a trade-off between low latency and high throughput, with increased latency due to processing overhead and resource contention in symmetric multiprocessing configurations, necessitating a method to optimize performance and latency dynamically.

Innovation Solution

A system and method that dynamically manage the assignment of operations by initially processing on a single core during initialization and then migrating tasks and interrupts to multiple cores, using a mapping to identify target cores for optimal load balancing and performance, allowing for rebalancing based on workload and resource availability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If operations are divided among multiple CPU cores in symmetric multiprocessing configuration, then throughput is improved, but latency increases due to processing overhead and resource contention

Engineering Contradiction:
ImprovethroughputVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic core assignment where the system can switch between single-core and multi-core modes based on workload characteristics. The migration mechanism dynamically moves tasks and ISRs between cores, allowing the system to adapt its processing architecture in real-time to optimize for either low latency or high throughput depending on current conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the processing workload by dividing it into tasks and interrupt service routines that can be independently assigned to different cores. This segmentation allows selective distribution of operations - time-critical ISRs can be handled on dedicated cores while less time-sensitive tasks can be parallelized across multiple cores, resolving the latency-throughput tradeoff

Inventive Principle:
Principle #1Segmentation

2Productivity

If tasks and interrupts are migrated between CPU cores, then load balancing and performance optimization are improved, but system complexity increases

Engineering Contradiction:
Improveperformance optimizationVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a migration mechanism that acts as an intermediary layer between the operating system and the CPU cores. This migration layer handles the complexity of task and ISR migration, core selection, and load balancing logic, shielding the rest of the system from these complexities while enabling performance optimization through dynamic core assignment

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If resource contention management mechanisms are implemented in multi-core systems, then resource management is improved, but processing overhead and latency increase

Engineering Contradiction:
Improveresource managementVSAvoidprocessing overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by assigning specific resource management responsibilities to specific cores. Dedicated cores handle time-critical interrupt service routines with minimal resource contention, while other cores handle less time-sensitive tasks. This localized resource management reduces the overhead of global resource contention mechanisms while maintaining reliable resource allocation

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3341839B1Migration between CPU cores
Publication Date: 2022.10.05 NETAPP INC
  • EP3341839B1 patent drawingFigure 1
  • EP3341839B1 patent drawingFigure 2
  • EP3341839B1 patent drawingFigure 3

AI summary

A method for migration of operations between CPU cores, the method includes: processing, by a source core, one or more tasks and one or more interrupt service routines; accessing a mapping corresponding to a task of the one or more tasks and an interrupt service routine of the one or more interrupt service routines; identifying, based on the mapping, a target core that corresponds to the task and the interrupt service routine; blocking the task from being processed by the source core in response to identifying the target core; in response to identifying the target core, disabling an interrupt corresponding to the interrupt service routine; in response to identifying the target core, assigning the task and the interrupt to the target core; after assigning the interrupt to the target core, enabling the interrupt; and after assigning the task to the target core, processing the task by the target core.